US 11,308,999 B2 · Boost bypass circuitry in a memory storage device

Abstract

The present disclosure describes various exemplary memory storage devices that can be programmed to bypass one or more memory cells in a bypass mode of operation. The various exemplary memory storage devices can adjust, for example, pull-up or pull-down, the electronic data as the electronic data passes through these exemplary memory storage devices in the bypass mode of operation. In some situations, the various exemplary memory storage devices may introduce an unwanted bias into the electronic data as the electronic data passes through these exemplary memory storage devices in the bypass mode of operation. The various exemplary memory storage devices can pull-down the electronic data and/or pull-up the electronic data as the electronic data is passing through these exemplary memory storage devices in the bypass mode of operation to compensate for this unwanted bias.

Claims20

Dependent claims

A memory storage device, comprising:

a memory cell, coupled to a bitline, configured to be deactivated in a bypass mode of operation;
a write driver configured to provide an input data bit to the bitline in the bypass mode of operation;
switch circuitry configured to couple the bitline to a data line to pass the input data bit on the bitline to the data line in the bypass mode of operation;
boost circuitry configured to adjust a potential level of the input data bit on the data line to be a potential level of the input data bit on the bitline in the bypass mode of operation;
and
a sense amplifier configured to read the input data bit on the data line to provide an output data bit in the bypass mode of operation.

3 more elements

Boost circuitry within a memory storage device, comprising:

a first logical INVERTER gate configured to perform a first logical inversion operation on a first input data bit on a first bitline;
a first switching element configured to adjust a voltage of a first output data bit on a first data line to be a potential level of an output of the first logical INVERTER gate;
a second logical INVERTER gate configured to perform a second logical inversion operation on a second input data bit on a second bitline, the second input data bit being a complement of the first input data bit;
a second switching element configured to adjust a voltage of a second output data bit on a second data line to be a potential level of an output of the second logical INVERTER gate, the second output data bit being a complement of the first output data bit;
and
one or more logic gates configured to activate or deactivate the first switching element and the second switching element based upon a presence of the first input data bit on the first bitline and the second input bit on the second bitline.

3 more elements

Dependencies are inferred from the claim text.

Facts

Application

17/128,831Filed 21 Dec 2020 · continuation

Priority

13 Jul 2018

Published

US 2021/0183418 A117 Jun 2021

Granted

19 Apr 2022

Term ends

Not estimatedThe source records don’t support an estimate.

Classification10 codes

G11C 7/12
Arrangements for writing information into, or reading information out from, a digital store: bit line control circuits, e.g. drivers, boosters,…
G11C 5/145
Power supply arrangements , e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels:…
G11C 7/08
Sense amplifiers; Associated circuits , e.g. timing or triggering circuits: control thereof
G11C 7/1063
Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits: control signal…

Family

Application62/697,667Us provisional application · filed 13 Jul 2018

Application16/502,596Parent of this continuation · filed 3 Jul 2019

US 2021/0183418 A1Pre-grant publication · published 17 Jun 2021

US 10,872,644 B2Parent of this continuation

US 2020/0020371 A1Published application

US 11,308,999 B2This patent

From the US filing history. Foreign family members aren’t listed.

Boost bypass circuitry in a memory storage device

Life of this patent

Boost bypass circuitry in a memory storage device

Life of this patent

Abstract

Claims20