Gate drive circuit for improving charging efficiency of display panel, display module and display device

A gate drive circuit, comprising:

• N array substrate row drive circuits arranged in cascade, wherein each array substrate row drive circuit comprises a signal input terminal, a pull-up control signal terminal and a gate drive signal output terminal, and an Nth array substrate row drive circuit is configured for outputting an Nth gate drive signal in response to a signal input terminal of the Nth array substrate row drive circuit receiving a gate drive signal output by an (N−1)th array substrate row drive circuit to control Nth sub-pixels to charge;
• and
• N auxiliary circuits, wherein each auxiliary circuit is arranged corresponding to one of the N array substrate row drive circuits, and each auxiliary circuit comprises a timing signal input terminal, a controlled terminal and an output terminal,
• wherein:
• a timing signal input terminal of an Nth auxiliary circuit is connected to an Nth timing control signal, a controlled terminal of the Nth auxiliary circuit is connected to a pull-up control signal terminal of the (N−1)th array substrate row drive circuit, and an output terminal of the Nth auxiliary circuit is connected to a gate drive signal output terminal of the Nth array substrate row drive circuit;
• and
• the Nth auxiliary circuit is configured for controlling the Nth sub-pixels to charge in a determination that the Nth timing control signal connected to the timing signal input terminal of the Nth auxiliary circuit and an (N−1)th pull-up control signal connected to the controlled terminal of the Nth auxiliary circuit are both high level, wherein N is an integer and greater than 1.