Shift register and driving method of shift register, gate driving circuit and display panel and device

A shift register, comprising:

• a first power signal input terminal, a second power signal input terminal, a first signal output terminal, a first node control device, a first output device, a first voltage stabilizing device and a first clock signal terminal;
• wherein
• a first terminal of the first voltage stabilizing device is electrically connected to an output terminal of the first node control device at a first node, a second terminal of the first voltage stabilizing device is electrically connected to a first control terminal of the first output device at a second node, and a control terminal of the first voltage stabilizing device is electrically connected to the first clock signal terminal;
• a first input terminal of the first output device is electrically connected to the first power signal input terminal, a second input terminal of the first output device is electrically connected to the second power signal input terminal, and an output terminal of the first output device is electrically connected to the first signal output terminal;
• in a display stage of a first frequency, the first voltage stabilizing device is configured to be turned on according to a control signal provided by the first clock signal terminal;
• or in a display stage of a second frequency, the first voltage stabilizing device is configured to be turned on or turned off according to a control signal provided by the first clock signal terminal;
• wherein the first frequency is greater than the second frequency;
• and
• wherein the display stage of the second frequency comprises a first sub-stage and a second sub-stage, and the first sub-stage corresponds to an initialization stage and a data signal writing stage of a pixel circuit, and the second sub-stage corresponds to a light emission stage of the pixel circuit;
• wherein
• in the first sub-stage, the first voltage stabilizing device is configured to be turned on according to the control signal provided by the first clock signal terminal;
• and
• in the second sub-stage, the first voltage stabilizing device is configured to be turned off according to the control signal provided by the first clock signal terminal.