Pixel circuit and driving method, pixel unit, display panel

A pixel circuit comprising:

• an input circuit respectively connected with N gate lines, a control line, and N control nodes, the input circuit being configured to control voltage levels of the N control nodes under control of a respective one gate-driving signal from a respective one of the N gate lines and under control of a first control signal from the control line;
• a control circuit respectively connected with the N control nodes and 2N switching nodes, the control circuit being configured to control a voltage level of a respective one of the 2N switching nodes under control of the N control nodes;
• and
• 2N output circuits respectively connected with 2N data-signal terminals, the 2N output circuits being connected with the 2N switching nodes, wherein an i-th output circuit of the 2N output circuits is coupled respectively with an i-th switching node of the 2N switching nodes, an i-th data-signal terminal of the 2N data-signal terminals, and an emission circuit, the i-th output circuit being configured to output an i-th data signal from the i-th data-signal terminal under control of the i-th switching node, wherein N is a positive integer, i is a positive integer no greater than N;
• wherein the N is 2;
• the control circuit includes a latch subcircuit, a first control subcircuit, and a second control subcircuit;
• the 2N switching nodes include a first switching node, a second switching node, a third switching node, and a fourth switching node;
• the N control nodes include a first control node and a second control node;
• the latch subcircuit being connected respectively to the first control node and a latch node configured to set a voltage level thereof under control of the first control node;
• the first control subcircuit being connected respectively to the latch node, the second control node, the first switching node, and a second switching node, the first control subcircuit being configured to respectively set voltage levels of the first switching node and the second switching node under control of the latch node and the second control node;
• the second control subcircuit being connected respectively to the first control node, the second control node, the third switching node, and the fourth switching node, the second control subcircuit being configured to respectively set voltage levels of the third switching node and the fourth switching node under control of the first control node and the second control node.