Shift register circuit and method of driving the same, gate driver circuit, array substrate and display device

A shift register circuit, comprising an input sub-circuit and a signal output sub-circuit, wherein the input sub-circuit comprises:

• a control module, the control module being connected with an input signal terminal and a first voltage terminal, and the control module being configured to output a signal of the first voltage terminal to a voltage dividing node under a control of an input signal provided by the input signal terminal;
• an input module, an input terminal of the input module being connected with the voltage dividing node, an output terminal of the input module being connected with the signal output sub-circuit, the input module being configured to output a signal of the voltage dividing node to the signal output sub-circuit under a control of the control module;
• and
• a voltage dividing module, a first terminal of the voltage dividing module being connected with the control module, a second terminal of the voltage dividing module being connected with a second voltage terminal, a resistance value of the voltage dividing module having a negative relationship with a temperature, and
• the signal output sub-circuit is connected with an output terminal of the input module, and the signal output sub-circuit is configured to output a gate scan signal from an output signal terminal under a control of the input module, wherein the input module comprises a first thin film transistor, a control terminal and a first terminal of, the first thin film transistor are connected with the voltage dividing node, and a second terminal of the first thin film transistor is connected with the signal output sub-circuit;
• wherein the signal output sub-circuit comprises a charging-discharging module, a second node holding module, a second node level changing module, a first node nose reduction module and a reset module, wherein
• a first input terminal of the charging-discharging module is connected with an output terminal of the input module and an output terminal of the first node noise reduction module at a first node, a second, input terminal of the charging-discharging module is connected with a first clock signal terminal, an output terminal of the charging-discharging module is connected with the output signal terminal, and the charging-discharging module is configured for performing a first charging operation under a combined action of an output signal of the first thin film transistor and a first clock signal provided by the first clock signal terminal, and performing a second charging operation and outputting a gate scan signal under an action of a potential of the first node and the first clock signal;
• a first input terminal of the second node holding module is connected with the second voltage terminal, a second input terminal of the second node holding module is connected with the first node, a first output terminal of the second node holding module is connected with a second input terminal of the second node level changing module, a second output terminal of the second node holding module is connected with an output terminal of the second node level changing, module, a third input terminal of the first node noise reduction module and a second input terminal of the reset module at a second node, and the second node holding module is configured for keeping a potential of the second node invalid under a combined action of the potential of the first node and an invalid potential signal provided by the second voltage terminal;
• a first, input terminal of the second node level changing module is connected with a second clock signal terminal, a second input terminal of the second node level changing module is connected with a first output terminal of the second node holding module, an output terminal of the second node level changing module is connected with the second node, and the second node level changing module is configured for changing the potential of the second node under a combined action of a second clock signal provided by the second clock signal terminal and an output signal of the second node holding module;
• a first input terminal of the first node noise reduction module is connected with the reset signal terminal, a second input terminal of the first node noise reduction module is connected with the second voltage terminal, a third input terminal of the first node noise reduction module is connected with the second node, an output terminal of the first node noise reduction module is connected with the first node, and the first node noise reduction module is configured for changing the potential of the first node under a combined action of a reset signal provided by the reset signal terminal, the invalid potential signal provided by the second voltage terminal and the potential of the second node;
• a first input terminal of the reset module is connected with the reset signal terminal, a second input terminal of the reset module is connected with the second node, a third input terminal of the reset module, is connected with the second voltage terminal, an output terminal of the reset module is connected with the output signal terminal, and the reset module is configured for resetting a potential of the output signal terminal under a combined action of the reset signal provided by the reset signal terminal, the potential of the second node and the invalid potential signal provided by the second voltage terminal;
• and
• the first clock signal has an inverted phase with respect to the second clock signal.