Signal generating circuit and display device

A display device, comprising:

• a substrate;
• a plurality of scan lines and a plurality of data lines disposed on the substrate;
• a gate driving circuit electrically connected to at least some of the scan lines, the gate driving circuit comprising:
• a starting signal line;
• a pull-down control signal line;
• a plurality of clock signal lines;
• and
• 1st to Nth stage shift registers, N is an integer greater than or equal to 4, each of the 1st to Nth stage shift registers having a main circuit unit and a discharge circuit unit, wherein the main circuit unit of each of the 1st to Nth stage shift registers includes a precharge unit and a pull-up unit, the precharge unit is configured to output a precharge signal to a first node, the pull-up unit is coupled to the precharge unit and is configured to receive the precharge signal, the pull-up unit is configured to output a scan signal to a second node, the pull-up unit includes a transistor, a first terminal of the transistor is coupled to the first node, a second terminal of the transistor is electrically connected to a corresponding clock signal line of the plurality of clock signal lines, and a third terminal of the transistor is coupled to the second node and is configured to output the scan signal, the discharge circuit units of at least some of the 1st to Nth stage shift registers are electrically connected to the pull-down control signal line, and wherein the precharge unit of the main circuit unit of the 1st stage shift register of the 1st to Nth stage shift registers is electrically connected to the starting signal line;
• and
• a signal generating circuit electrically connected to the gate driving circuit, the signal generating circuit comprising:
• an inverter having an input node and an output node;
• a level shifter having a starting signal input terminal, a pull-down control signal input terminal, a plurality of clock signal input terminals, a starting signal output terminal, a pull-down control signal output terminal and a plurality of clock signal output terminals, the pull-down control signal input terminal of the level shifter being coupled to the output node of the inverter, and the starting signal output terminal, the pull-down control signal output terminal and the clock signal output terminals of the level shifter being coupled to the starting signal line, the pull-down control signal line and the clock signal lines, respectively;
• and
• a timing controller coupled to the input node of the inverter and the starting signal input terminal and the clock signal input terminals of the level shifter, wherein the timing controller is configured to provide a first pull-down control signal, a first starting signal and a plurality of first clock signals respectively to the input node of the inverter and the starting signal input terminal and the clock signal input terminals of the level shifter;
• wherein:
• the inverter is configured to convert the first pull-down control signal into another first pull-down control signal and transmit the another first pull-down control signal to the pull-down control signal input terminal of the level shifter, and the another first pull-down control signal is phase-inverted to the first pull-down control signal and is a triggering signal of the level shifter, wherein after the display device is powered on or restarts and before the display device displays a first frame, the first pull-down control signal is at a disabling voltage level, and the inverter converts the first pull-down control signal having the disabling voltage level into the another first pull-down control signal having an enabling voltage level;
• the level shifter is configured to convert the another first pull-down control signal, the first starting signal and the first clock signals respectively into a second pull-down control signal, a second starting signal and a plurality of second clock signals, a voltage level of each of the second pull-down control signal, the second starting signal and the second clock signals is between a gate high voltage and a gate low voltage, and the level shifter is configured to transmit the second pull-down control signal, the second starting signal and the second clock signals respectively to the pull-down control signal output terminal, the starting signal output terminal and the clock signal output terminals, wherein after the display device is powered on or restarts, the second starting signal switches from a disabling voltage level to an enabling voltage level at a first time point, and the second pull-down control signal switches from a disabling voltage level to an enabling voltage level at a second time point that is before the first time point;
• the pull-down control signal line is configured to receive the second pull-down control signal through the pull-down control signal output terminal of the level shifter and transmit the second pull-down control signal to the discharge circuit units of the at least some of the 1st to Nth stage shift registers;
• the starting signal line is configured to receive the second starting signal through the starting signal output terminal of the level shifter and transmit the second starting signal to the precharge unit of the main circuit unit of the 1st stage shift register of the 1st to Nth stage shift registers;
• and
• the clock signal lines are configured to receive the second clock signals through the clock signal output terminals of the level shifter and transmit the second clock signals to the pull-up units of the main circuit units of the 1st to Nth stage shift registers.