Neural network layer-by-layer debugging

A method of debugging a neural network execution on a target processor, the method comprising:

• receiving a plurality of first reference tensors for a neural network;
• repeatedly reducing a plurality of layers of the neural network to produce a plurality of reduced lengths, and for each particular reduced length of the plurality of reduced lengths:
• converting, by a compiler, the neural network having the particular reduced length into first machine instructions;
• executing, using the target processor, the first machine instructions to generate a first device tensor;
• and
• determining whether the first device tensor matches a first reference tensor of the plurality of first reference tensors;
• identifying a shortened length of the plurality of reduced lengths for which the first device tensor does not match the first reference tensor;
• generating a plurality of second reference tensors for a representation of the neural network having the shortened length;
• converting, by the compiler, the neural network having the shortened length into second machine instructions;
• and
• executing, using the target processor, the second machine instructions to generate a second device tensor for the representation.

A non-transitory computer-readable medium comprising instructions that, when executed by one or more processors, cause the one or more processors to perform operations including:

• receiving a plurality of first reference tensors for a neural network;
• repeatedly reducing a plurality of layers of the neural network to produce a plurality of reduced lengths, and for each particular reduced length of the plurality of reduced lengths:
• converting, by a compiler, the neural network having the particular reduced length into first machine instructions;
• executing, using a target processor, the first machine instructions to generate a first device tensor;
• and
• determining whether the first device tensor matches a first reference tensor of the plurality of first reference tensors;
• identifying a shortened length of the plurality of reduced lengths for which the first device tensor does not match the first reference tensor;
• generating a plurality of second reference tensors for a representation of the neural network having the shortened length;
• converting, by the compiler, the neural network having the shortened length into second machine instructions;
• and
• executing, using a target processor, the second machine instructions to generate a second device tensor for the representation.