Integrated circuit chip apparatus
AssigneeCambricon Technologies Corporation Limited
InventorsShaoli Liu, Xinkai Song, Bingrui Wang, Yao Zhang, Shuai Hu
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Abstract
Provided are an integrated circuit chip apparatus and a related product, the integrated circuit chip apparatus being used for executing a multiplication operation, a convolution operation or a training operation of a neural network. The present technical solution has the advantages of a small amount of calculation and low power consumption.
Claims19
An integrated circuit chip apparatus, comprising:
- a main processing circuit;
- and
- a plurality of basic processing circuits arranged in a form of an m*n array comprising m rows and n columns of basic processing circuits, wherein each basic processing circuit is connected to its adjacent basic processing circuits in the array, and the main processing circuit is connected to k basic processing circuits of the plurality of basic processing circuits arranged on one or more sides of the array, wherein the plurality of basic processing circuits comprise data type conversion circuits configured to convert data between a floating data type and a fixed point data type,
- wherein the main processing circuit is configured to transfer data and a computation instruction to the k basic processing circuits, wherein the data comprises a broadcast data block and a plurality of basic data blocks partitioned from a data block to be computed,
- wherein to transfer the data to the k basic processing circuits, the main processor is further configured to:
- distribute the plurality of basic data blocks to the k basic processing circuits;
- and
- broadcast the broadcasting data block to the k basic processing circuits,
- wherein the k basic processing circuits are configured to forward data received from the main processing circuit to the other basic processing circuits among the plurality of basic processing circuits,
- wherein the plurality of basic processing circuits are configured to determine whether to convert the data transferred between the floating point data type and the fixed point data type according to the type of the data transferred and the computation instruction, perform a first set of neural network computations in parallel on the data transferred, and transfer computation results to the main processing circuit through the k basic processing circuits,
- wherein the main processing circuit is further configured to perform a second set of neural network computations in series on the computation results.
A processing system, comprising:
- a neural network computing apparatus;
- a general interconnection interface;
- and
- a general-purpose processing apparatus connected to the neural network computing apparatus via the general interconnection interface,
- wherein the neural network computing apparatus further comprises:
- a main processing circuit;
- and
- a plurality of basic processing circuits arranged in a form of an m*n array comprising m rows and n columns of basic processing circuits, wherein each basic processing circuit is connected to its adjacent basic processing circuits in the array, and the main processing circuit is connected to k basic processing circuits of the plurality of basic processing circuits arranged on one or more sides of the array, wherein the plurality of basic processing circuits comprise data type conversion circuits configured to convert data between a floating data type and a fixed point data type,
- wherein the main processing circuit is configured to transfer data and a computation instruction to the k basic processing circuits,
- wherein the k basic processing circuits are configured to forward data received from the main processing circuit to the other basic processing circuits among the plurality of basic processing circuits, wherein the data forwarded by the k basic processing circuits is in the floating point data type,
- wherein the plurality of basic processing circuits are configured to determine that the data forwarded should be converted, convert the data forwarded into the fixed point data type, perform a first set of neural network computations in parallel in the fixed point data type on the data forwarded to obtain the computation results in the fixed point data type, and transfer computation results to the main processing circuit through the k basic processing circuits,
- wherein the main processing circuit is further configured to perform a second set of neural network computations in series on the computation results.
A method for performing neural network operations using an integrated circuit chip apparatus comprising a main processing circuit, and a plurality of basic processing circuits arranged in a form of an m*n array comprising m rows and n columns of basic processing circuits, wherein each basic processing circuit is connected to its adjacent basic processing circuits in the array, and the main processing circuit is connected to k basic processing circuits of the plurality of basic processing circuits arranged on one or more sides of the array, wherein the plurality of basic processing circuits comprise data type conversion circuits configured to convert data between a floating data type and a fixed point data type, the method comprising:
- transferring data and a computation instruction from the main processing circuit to the k basic processing circuits;
- forwarding, by the k basic processing circuits, data received from the main processing circuit to the other basic processing circuits among the plurality of basic processing circuits, wherein the data forwarded by the k basic processing circuits is in the floating point data type;
- determining, by the plurality of basic processing circuits, that the data forwarded should be converted;
- converting, by the plurality of basic processing circuits, the data forwarded into the fixed point data type;
- performing, by the plurality of basic processing circuits, a first set of neural network computations in parallel in the fixed point data type on the data forwarded to obtain the computation results in the fixed point data type;
- transferring the computation results to the main processing circuit through the k basic processing circuits;
- and
- performing, by the main processing circuit, a second set of neural network computations in series on the computation results.
Dependencies are inferred from the claim text.