US 11,308,383 B2 · Deep learning neural network classifier using non-volatile memory array · patentgrep

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Abstract

An artificial neural network device that utilizes one or more non-volatile memory arrays as the synapses. The synapses are configured to receive inputs and to generate therefrom outputs. Neurons are configured to receive the outputs. The synapses include a plurality of memory cells, wherein each of the memory cells includes spaced apart source and drain regions formed in a semiconductor substrate with a channel region extending there between, a floating gate disposed over and insulated from a first portion of the channel region and a non-floating gate disposed over and insulated from a second portion of the channel region. Each of the plurality of memory cells is configured to store a weight value corresponding to a number of electrons on the floating gate. The plurality of memory cells are configured to multiply the inputs by the stored weight values to generate the outputs.

Claims20

Dependent claims

A neural network device, comprising:

a first plurality of synapses configured to receive a first plurality of inputs and to generate therefrom a first plurality of outputs, wherein the first plurality of synapses comprises:
a plurality of memory cells, wherein each of the memory cells includes spaced apart source and drain regions formed in a semiconductor substrate with a channel region extending there between, a floating gate disposed over and insulated from a first portion of the channel region, a first non-floating gate disposed over and insulated from a second portion of the channel region and configured to receive the first plurality of inputs, a second non-floating gate disposed over and insulated from the source region, and a third non-floating gate disposed over and insulated from the floating gate;
each of the plurality of memory cells is configured to store a weight value corresponding to a number of electrons on the floating gate;
the plurality of memory cells are configured to multiply the first plurality of inputs by the stored weight values to generate the first plurality of outputs;
a first plurality of neurons configured to receive the first plurality of outputs;
wherein the memory cells of the first plurality of synapses are arranged in rows and columns, and wherein the first plurality of synapses comprises:
a plurality of first lines each electrically connecting together the first non-floating gates of odd row memory cells in one of the columns of the memory cells;
a plurality of second lines each electrically connecting together the first non-floating gates of even row memory cells in one of the columns of the memory cells;
a plurality of third lines each electrically connecting together the second non-floating gates in one of the columns of the memory cells;
a plurality of fourth lines each electrically connecting together the third non-floating gates in one of the rows of the memory cells;
a plurality of fifth lines each electrically connecting together the source regions in one of the rows of the memory cells;
a plurality of sixth lines each electrically connecting together the drain regions in one of the columns of the memory cells;
wherein the first plurality of synapses is configured to receive some of the first plurality of inputs on the plurality of first lines and others of the first plurality of inputs on the plurality of second lines, and to provide the first plurality of outputs on the plurality of fifth lines.

10 more elements

A neural network device, comprising:

a first plurality of synapses configured to receive a first plurality of inputs and to generate therefrom a first plurality of outputs, wherein the first plurality of synapses comprises:
a plurality of memory cells, wherein each of the memory cells includes spaced apart source and drain regions formed in a semiconductor substrate with a channel region extending there between, a floating gate disposed over and insulated from a first portion of the channel region, a first non-floating gate disposed over and insulated from a second portion of the channel region and configured to receive the first plurality of inputs, a second non-floating gate disposed over and insulated from the source region, and a third non-floating gate disposed over and insulated from the floating gate;
each of the plurality of memory cells is configured to store a weight value corresponding to a number of electrons on the floating gate;
the plurality of memory cells are configured to multiply the first plurality of inputs by the stored weight values to generate the first plurality of outputs;
a first plurality of neurons configured to receive the first plurality of outputs;
wherein the memory cells of the first plurality of synapses are arranged in rows and columns, and wherein the first plurality of synapses comprises:
a plurality of first lines each electrically connecting together the first non-floating gates of odd row memory cells in one of the columns of the memory cells;
a plurality of second lines each electrically connecting together the first non-floating gates of even row memory cells in one of the columns of the memory cells;
a plurality of third lines each electrically connecting together the second non-floating gates in one of the columns of the memory cells;
a plurality of fourth lines each electrically connecting together the third non-floating gates in one of the rows of the memory cells;
a plurality of fifth lines each electrically connecting together the source regions in one of the rows of the memory cells;
a plurality of sixth lines each electrically connecting together odd drain regions in one of the columns of the memory cells;
a plurality of seventh lines each electrically connecting together even drain regions in one of the columns of the memory cells;
wherein the first plurality of synapses is configured to receive some of the first plurality of inputs on the plurality of first lines and others of the first plurality of inputs on the plurality of second lines, and to provide the first plurality of outputs on the plurality of fifth lines.

11 more elements

A neural network device, comprising:

a first plurality of synapses configured to receive a first plurality of inputs and to generate therefrom a first plurality of outputs, wherein the first plurality of synapses comprises:
a plurality of memory cells, wherein each of the memory cells includes spaced apart source and drain regions formed in a semiconductor substrate with a channel region extending there between, a floating gate disposed over and insulated from a first portion of the channel region, a first non-floating gate disposed over and insulated from a second portion of the channel region and configured to receive the first plurality of inputs, a second non-floating gate disposed over and insulated from the source region, and a third non-floating gate disposed over and insulated from the floating gate;
each of the plurality of memory cells is configured to store a weight value corresponding to a number of electrons on the floating gate;
the plurality of memory cells are configured to multiply the first plurality of inputs by the stored weight values to generate the first plurality of outputs;
a first plurality of neurons configured to receive the first plurality of outputs;
wherein the memory cells of the first plurality of synapses are arranged in rows and columns, and wherein the first plurality of synapses comprises:
a plurality of first lines each electrically connecting together the first non-floating gates of odd row memory cells in one of the columns of the memory cells;
a plurality of second lines each electrically connecting together the first non-floating gates of even row memory cells in one of the columns of the memory cells;
a plurality of third lines each electrically connecting together the second non-floating gates in one of the row of the memory cells;
a plurality of fourth lines each electrically connecting together the third non-floating gates of odd row memory cells in one of the columns of the memory cells;
a plurality of fifth lines each electrically connecting together the third non-floating gates of even row memory cells in one of the columns of the memory cells;
a plurality of sixth lines each electrically connecting together the source regions in one of the rows of the memory cells;
a plurality of seventh lines each electrically connecting together odd drain regions in one of the columns of the memory cells;
a plurality of eighth lines each electrically connecting together even drain regions in one of the columns of the memory cells;
wherein the first plurality of synapses is configured to receive some of the first plurality of inputs on the plurality of first lines and others of the first plurality of inputs on the plurality of second lines, and to provide the first plurality of outputs on the plurality of sixth lines.

12 more elements

A neural network device, comprising:

a first plurality of synapses configured to receive a first plurality of inputs and to generate therefrom a first plurality of outputs, wherein the first plurality of synapses comprises:
a plurality of memory cells, wherein each of the memory cells includes spaced apart source and drain regions formed in a semiconductor substrate with a channel region extending there between, a floating gate disposed over and insulated from a first portion of the channel region, and a first non-floating gate disposed over and insulated from a second portion of the channel region and configured to receive the first plurality of inputs;
each of the plurality of memory cells is configured to store a weight value corresponding to a number of electrons on the floating gate;
the plurality of memory cells are configured to multiply the first plurality of inputs by the stored weight values to generate the first plurality of outputs;
a first plurality of neurons configured to receive the first plurality of outputs;
wherein the memory cells of the first plurality of synapses are arranged in rows and columns, and wherein the first plurality of synapses comprises:
a plurality of first lines each electrically connecting together the first non-floating gates of odd row memory cells in one of the columns of the memory cells;
a plurality of second lines each electrically connecting together the first non-floating gates of even row memory cells in one of the columns of the memory cells;
a plurality of third lines each electrically connecting together the source regions in one of the rows of the memory cells;
a plurality of fourth lines each electrically connecting together the drain regions in one of the columns of the memory cells;
wherein the first plurality of synapses is configured to receive some of the first plurality of inputs on the plurality of first lines and others of the first plurality of inputs on the plurality of second lines, and to provide the first plurality of outputs on the plurality of third lines.

8 more elements

A neural network device, comprising:

a first plurality of synapses configured to receive a first plurality of inputs and to generate therefrom a first plurality of outputs, wherein the first plurality of synapses comprises:
a plurality of memory cells, wherein each of the memory cells includes spaced apart source and drain regions formed in a semiconductor substrate with a channel region extending there between, a floating gate disposed over and insulated from a first portion of the channel region, a first non-floating gate disposed over and insulated from a second portion of the channel region and configured to receive the first plurality of inputs, a second non-floating gate disposed over and insulated from the source region, and a third non-floating gate disposed over and insulated from the floating gate;
each of the plurality of memory cells is configured to store a weight value corresponding to a number of electrons on the floating gate;
the plurality of memory cells are configured to multiply the first plurality of inputs by the stored weight values to generate the first plurality of outputs;
a first plurality of neurons configured to receive the first plurality of outputs;
wherein the memory cells of the first plurality of synapses are arranged in rows and columns, and wherein the first plurality of synapses comprises:
a plurality of first lines each electrically connecting together some but not all of the first non-floating gates in one of the rows of the memory cells and some but not all of the first non-floating gates in another one of the rows of the memory cells;
a plurality of second lines each electrically connecting together the second non-floating gates in one of the columns of the memory cells;
a plurality of third lines each electrically connecting together the third non-floating gates in one of the rows of the memory cells;
a plurality of fourth lines each electrically connecting together the source regions in one of the rows of the memory cells;
a plurality of fifth lines each electrically connecting together the drain regions in one of the columns of the memory cells;
wherein the first plurality of synapses is configured to receive the first plurality of inputs on the plurality of first lines, and to provide the first plurality of outputs on the plurality of fifth lines.

9 more elements

A neural network device, comprising:

a first plurality of synapses configured to receive a first plurality of inputs and to generate therefrom a first plurality of outputs, wherein the first plurality of synapses comprises:
a plurality of memory cells, wherein each of the memory cells includes spaced apart source and drain regions formed in a semiconductor substrate with a channel region extending there between, a floating gate disposed over and insulated from a first portion of the channel region, a first non-floating gate disposed over and insulated from a second portion of the channel region and configured to receive the first plurality of inputs, a second non-floating gate disposed over and insulated from the source region, and a third non-floating gate disposed over and insulated from the floating gate;
each of the plurality of memory cells is configured to store a weight value corresponding to a number of electrons on the floating gate;
the plurality of memory cells are configured to multiply the first plurality of inputs by the stored weight values to generate the first plurality of outputs;
a first plurality of neurons configured to receive the first plurality of outputs;
wherein the memory cells of the first plurality of synapses are arranged in rows and columns, and wherein the first plurality of synapses comprises:
a plurality of first lines each electrically connecting together some but not all of the first non-floating gates in one of the rows of the memory cells and some but not all of the first non-floating gates in another one of the rows of the memory cells;
a plurality of second lines each electrically connecting together the second non-floating gates in one of the rows of the memory cells;
a plurality of third lines each electrically connecting together the third non-floating gates in one of the rows of the memory cells;
a plurality of fourth lines each electrically connecting together the source regions in one of the columns of the memory cells;
a plurality of fifth lines each electrically connecting together the drain regions in one of the columns of the memory cells;
wherein the first plurality of synapses is configured to receive the first plurality of inputs on the plurality of first lines, and to provide the first plurality of outputs on the plurality of fifth lines.

9 more elements

A neural network device, comprising:

a first plurality of synapses configured to receive a first plurality of inputs and to generate therefrom a first plurality of outputs, wherein the first plurality of synapses comprises:
a plurality of memory cells, wherein each of the memory cells includes spaced apart source and drain regions formed in a semiconductor substrate with a channel region extending there between, a floating gate disposed over and insulated from a first portion of the channel region, a first non-floating gate disposed over and insulated from a second portion of the channel region and configured to receive the first plurality of inputs, a second non-floating gate disposed over and insulated from the source region, and a third non-floating gate disposed over and insulated from the floating gate;
each of the plurality of memory cells is configured to store a weight value corresponding to a number of electrons on the floating gate;
the plurality of memory cells are configured to multiply the first plurality of inputs by the stored weight values to generate the first plurality of outputs;
a first plurality of neurons configured to receive the first plurality of outputs;
wherein the memory cells of the first plurality of synapses are arranged in rows and columns, and wherein the first plurality of synapses comprises:
a plurality of first lines each electrically connecting together some but not all of the first non-floating gates of odd row memory cells in one of the columns of the memory cells and some but not all of the first non-floating gates of odd row memory cells in another one of the columns of the memory cells;
a plurality of second lines each electrically connecting together some but not all of the first non-floating gates of even row memory cells in one of the columns of the memory cells and some but not all of the first non-floating gates of even row memory cells in another one of the columns of the memory cells;
a plurality of third lines each electrically connecting together the second non-floating gates in one of the columns of the memory cells;
a plurality of fourth lines each electrically connecting together the third non-floating gates in one of the rows of the memory cells;
a plurality of fifth lines each electrically connecting together the source regions in one of the rows of the memory cells;
a plurality of sixth lines each electrically connecting together the drain regions in one of the columns of the memory cells;
wherein the first plurality of synapses is configured to receive some of the first plurality of inputs on the plurality of first lines and others of the first plurality of inputs on the plurality of second lines, and to provide the first plurality of outputs on the plurality of fifth lines.

10 more elements

A neural network device, comprising:

a first plurality of synapses configured to receive a first plurality of inputs and to generate therefrom a first plurality of outputs, wherein the first plurality of synapses comprises:
a plurality of memory cells, wherein each of the memory cells includes spaced apart source and drain regions formed in a semiconductor substrate with a channel region extending there between, a floating gate disposed over and insulated from a first portion of the channel region, a first non-floating gate disposed over and insulated from a second portion of the channel region and configured to receive the first plurality of inputs, a second non-floating gate disposed over and insulated from the source region, and a third non-floating gate disposed over and insulated from the floating gate;
each of the plurality of memory cells is configured to store a weight value corresponding to a number of electrons on the floating gate;
the plurality of memory cells are configured to multiply the first plurality of inputs by the stored weight values to generate the first plurality of outputs;
a first plurality of neurons configured to receive the first plurality of outputs;
wherein the memory cells of the first plurality of synapses are arranged in rows and columns, and wherein the first plurality of synapses comprises:
a plurality of first lines each electrically connecting together some but not all of the first non-floating gates of odd row memory cells in one of the columns of the memory cells and some but not all of the first non-floating gates of odd row memory cells in another one of the columns of the memory cells;
a plurality of second lines each electrically connecting together some but not all of the first non-floating gates of even row memory cells in one of the columns of the memory cells and some but not all of the first non-floating gates of even row memory cells in another one of the columns of the memory cells;
a plurality of third lines each electrically connecting together the second non-floating gates in one of the columns of the memory cells;
a plurality of fourth lines each electrically connecting together the third non-floating gates in one of the rows of the memory cells;
a plurality of fifth lines each electrically connecting together the source regions in one of the rows of the memory cells;
a plurality of sixth lines each electrically connecting together odd drain regions in one of the columns of the memory cells;
a plurality of seventh lines each electrically connecting together even drain regions in one of the columns of the memory cells;
wherein the first plurality of synapses is configured to receive some of the first plurality of inputs on the plurality of first lines and others of the first plurality of inputs on the plurality of second lines, and to provide the first plurality of outputs on the plurality of fifth lines.

11 more elements

A neural network device, comprising:

a first plurality of synapses configured to receive a first plurality of inputs and to generate therefrom a first plurality of outputs, wherein the first plurality of synapses comprises:
a plurality of memory cells, wherein each of the memory cells includes spaced apart source and drain regions formed in a semiconductor substrate with a channel region extending there between, a floating gate disposed over and insulated from a first portion of the channel region, a first non-floating gate disposed over and insulated from a second portion of the channel region and configured to receive the first plurality of inputs, a second non-floating gate disposed over and insulated from the source region, and a third non-floating gate disposed over and insulated from the floating gate;
each of the plurality of memory cells is configured to store a weight value corresponding to a number of electrons on the floating gate;
the plurality of memory cells are configured to multiply the first plurality of inputs by the stored weight values to generate the first plurality of outputs;
a first plurality of neurons configured to receive the first plurality of outputs;
wherein the memory cells of the first plurality of synapses are arranged in rows and columns, and wherein the first plurality of synapses comprises:
a plurality of first lines each electrically connecting together some but not all of the first non-floating gates of odd row memory cells in one of the columns of the memory cells and some but not all of the first non-floating gates of odd row memory cells in another one of the columns of the memory cells;
a plurality of second lines each electrically connecting together some but not all of the first non-floating gates of even row memory cells in one of the columns of the memory cells and some but not all of the first non-floating gates of even row memory cells in another one of the columns of the memory cells;
a plurality of third lines each electrically connecting together the second non-floating gates in one of the row of the memory cells;
a plurality of fourth lines each electrically connecting together the third non-floating gates of odd row memory cells in one of the columns of the memory cells;
a plurality of fifth lines each electrically connecting together the third non-floating gates of even row memory cells in one of the columns of the memory cells;
a plurality of sixth lines each electrically connecting together the source regions in one of the rows of the memory cells;
a plurality of seventh lines each electrically connecting together odd drain regions in one of the columns of the memory cells;
a plurality of eighth lines each electrically connecting together even drain regions in one of the columns of the memory cells;
wherein the first plurality of synapses is configured to receive some of the first plurality of inputs on the plurality of first lines and others of the first plurality of inputs on the plurality of second lines, and to provide the first plurality of outputs on the plurality of sixth lines.

12 more elements

A neural network device, comprising:

a first plurality of synapses configured to receive a first plurality of inputs and to generate therefrom a first plurality of outputs, wherein the first plurality of synapses comprises:
a plurality of memory cells, wherein each of the memory cells includes spaced apart source and drain regions formed in a semiconductor substrate with a channel region extending there between, a floating gate disposed over and insulated from a first portion of the channel region, a first non-floating gate disposed over and insulated from a second portion of the channel region and configured to receive the first plurality of inputs, a second non-floating gate disposed over and insulated from the source region, and a third non-floating gate disposed over and insulated from the floating gate;
each of the plurality of memory cells is configured to store a weight value corresponding to a number of electrons on the floating gate;
the plurality of memory cells are configured to multiply the first plurality of inputs by the stored weight values to generate the first plurality of outputs;
a first plurality of neurons configured to receive the first plurality of outputs;
wherein the memory cells of the first plurality of synapses are arranged in rows and columns, and wherein the first plurality of synapses comprises:
a plurality of first lines each electrically connecting together some but not all of the first non-floating gates in one of the rows of the memory cells and some but not all of the first non-floating gates in another one of the rows of the memory cells;
a plurality of second lines each electrically connecting together the second non-floating gates in one of the rows of the memory cells;
a plurality of third lines each electrically connecting together the third non-floating gates in one of the rows of the memory cells;
a plurality of fourth lines each electrically connecting together the source regions in one of the columns of the memory cells;
a plurality of fifth lines each electrically connecting together the drain regions in one of the columns of the memory cells;
wherein the first plurality of synapses is configured to receive the first plurality of inputs on the plurality of first lines, and to provide the first plurality of outputs on the plurality of fourth lines.

9 more elements

A neural network device, comprising:

a first plurality of synapses configured to receive a first plurality of inputs and to generate therefrom a first plurality of outputs, wherein the first plurality of synapses comprises:
a plurality of memory cells, wherein each of the memory cells includes spaced apart source and drain regions formed in a semiconductor substrate with a channel region extending there between, a floating gate disposed over and insulated from a first portion of the channel region, and a first non-floating gate disposed over and insulated from a second portion of the channel region and configured to receive the first plurality of inputs;
each of the plurality of memory cells is configured to store a weight value corresponding to a number of electrons on the floating gate;
the plurality of memory cells are configured to multiply the first plurality of inputs by the stored weight values to generate the first plurality of outputs;
a first plurality of neurons configured to receive the first plurality of outputs;
wherein the memory cells of the first plurality of synapses are arranged in rows and columns, and wherein the first plurality of synapses comprises:
a plurality of first lines each electrically connecting together some but not all of the first non-floating gates in one of the rows of the memory cells and some but not all of the first non-floating gates in another one of the rows of the memory cells;
a plurality of second lines each electrically connecting together the source regions in one of the columns of the memory cells;
a plurality of third lines each electrically connecting together the drain regions in one of the columns of the memory cells;
wherein the first plurality of synapses is configured to receive the first plurality of inputs on the plurality of first lines, and to provide the first plurality of outputs on the plurality of third lines.

7 more elements

A neural network device, comprising:

a first plurality of synapses configured to receive a first plurality of inputs and to generate therefrom a first plurality of outputs, wherein the first plurality of synapses comprises:
a plurality of memory cells, wherein each of the memory cells includes spaced apart source and drain regions formed in a semiconductor substrate with a channel region extending there between, a floating gate disposed over and insulated from a first portion of the channel region, and a first non-floating gate disposed over and insulated from a second portion of the channel region and configured to receive the first plurality of inputs;
each of the plurality of memory cells is configured to store a weight value corresponding to a number of electrons on the floating gate;
the plurality of memory cells are configured to multiply the first plurality of inputs by the stored weight values to generate the first plurality of outputs;
a first plurality of neurons configured to receive the first plurality of outputs;
wherein the memory cells of the first plurality of synapses are arranged in rows and columns, and wherein the first plurality of synapses comprises:
a plurality of first lines each electrically connecting together some but not all of the first non-floating gates of odd row memory cells in one of the columns of the memory cells and some but not all of the first non-floating gates of odd row memory cells in another one of the columns of the memory cells;
a plurality of second lines each electrically connecting together some but not all of the first non-floating gates of even row memory cells in one of the columns of the memory cells and some but not all of the first non-floating gates of even row memory cells in another one of the columns of the memory cells;
a plurality of third lines each electrically connecting together the source regions in one of the rows of the memory cells;
a plurality of fourth lines each electrically connecting together the drain regions in one of the columns of the memory cells;
wherein the first plurality of synapses is configured to receive some of the first plurality of inputs on the plurality of first lines and others of the first plurality of inputs on the plurality of second lines, and to provide the first plurality of outputs on the plurality of third lines.

8 more elements

Dependencies are inferred from the claim text.

Facts

Application: 15/594,439Filed 12 May 2017 · us provisional application
Priority: 17 May 2016
Published: US 2017/0337466 A123 Nov 2017
Granted: 19 Apr 2022
Term ends: Not estimatedThe source records don’t support an estimate.

Classification18 codes

G06N 3/065
Using electronic means: analogue means
G06F 3/061
Specifically adapted to achieve a particular effect: improving I/O performance
G06F 3/0655
Making use of a particular technique: vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more…
G06F 3/0688
Plurality of storage devices: non-volatile semiconductor memory arrays

Family

Application62/337,760Us provisional application · filed 17 May 2016
US 2017/0337466 A1Pre-grant publication · published 23 Nov 2017
US 11,308,383 B2This patent

From the US filing history. Foreign family members aren’t listed.

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