Method of post optical proximity correction (OPC) printing verification by machine learning

A system of fabricating an integrated circuit (IC), comprising:

• at least memory storing a database;
• a mask making module configured to receive an IC design layout, wherein the mask making module comprises:
• a data preparation module configured to:
• perform an optical proximity correction (OPC) process to the IC design layout to produce a corrected IC design layout, and
• verify the corrected IC design layout using a machine learning algorithm to identify and compare one or more features of the corrected IC design layout with the database comprising a plurality of features, and
• verify the corrected IC design layout based on labels in the database associated with the plurality of features;
• a mask tooling module configured to print the mask layout design;
• a fabrication module configured to fabricate the IC using the mask,
• wherein the labels correspond to a probability of whether the corrected IC design will print-out successfully on a wafer or print with defects on the wafer.

A computer readable medium having computer executable code stored thereon, comprising:

• code for receiving an integrated circuit (IC) design layout;
• code for performing an optical proximity correction (OPC) process to the IC design layout to produce a corrected IC design layout;
• code for verifying the corrected IC design layout, wherein the code for verifying the corrected IC design layout comprises code for using a machine learning algorithm to identify and compare one or more features of the corrected IC design layout with the database comprising a plurality of features;
• and
• code for generating a database, comprising:
• code for generating a plurality of IC design layouts,
• code for simulating each of the plurality of IC design layouts to determine a probability of whether the corrected IC design will print-out successfully on a wafer or print with defects on the wafer, and
• code for storing a label associated with each of the simulated IC design layouts in the database, wherein the label indicates the probability of whether the corrected IC design will print-out successfully on a wafer or print with defects on the wafer.