Partitioning in post-layout circuit simulation

A system comprising:

• a memory storing instructions;
• and
• a processor, coupled with the memory and to execute the instructions, the instructions when executed cause the processor to:
• access a shared database storing a pre-layout circuit netlist of an integrated circuit design and a post-layout circuit netlist of the integrated circuit design;
• the post-layout circuit netlist comprising one or more rail blocks, one or more power nets that do not belong to the rail blocks, and one or more signal nets;
• wherein the rail blocks includes a voltage source, the power nets drive the signal nets from the rail blocks, and the post-layout circuit netlist comprises parasitic RC circuit elements produced by RC extraction applied to the integrated circuit design;
• partition the signal nets into signal blocks supplied by the rail blocks and/or power nets, wherein partitioning into the signal blocks is based on the parasitic RC circuit elements produced by the RC extraction and on a partitioning of the pre-layout circuit netlist;
• and
• apply a circuit simulation to sub-circuits defined by the partitioned signal blocks of the post-layout circuit netlist.

A non-transitory computer readable medium comprising stored instructions, which when executed by a processor, cause the processor to:

• receive a post-layout circuit netlist of an integrated circuit design;
• the post-layout circuit netlist comprising one or more rail blocks, one or more power nets that do not belong to the rail blocks, and one or more signal nets;
• wherein the rail blocks includes a voltage source, the power nets drive the signal nets from the rail blocks, and the post-layout circuit netlist comprises parasitic RC circuit elements produced by RC extraction applied to the integrated circuit design;
• partition, by a processor, the signal nets into signal blocks supplied by the rail blocks and/or power nets, wherein partitioning the signal blocks is based on a partitioning of a pre-layout circuit netlist of the integrated circuit design;
• and
• apply a circuit simulation to sub-circuits defined by the partitioned signal blocks.