Multiple busses interleaved in a systolic array

A systolic circuit comprising:

• a systolic array comprising a plurality of processing elements arranged into rows and columns, each row of the systolic array including a plurality of row-oriented buses, each row-oriented bus configured to pass data along a set of processing elements in non-adjacent columns for use in the performance of mathematical operations by the set of processing elements corresponding to the row-oriented bus, each processing element within an individual column of the systolic array configured to:
• receive a respective weight and a respective input data element,
• perform one or more operations on the weight and the input data element, and
• provide the weight and the input data element to a processing element of a subsequent column corresponding to the row-oriented bus of the individual column, wherein the subsequent column is separated within the systolic array from the individual column by one or more intervening columns corresponding to a different row-oriented bus.

A method comprising:

• receiving a first weight corresponding to a first row-oriented bus of a row of a systolic array and a second weight corresponding to a second row-oriented bus of the row of the systolic array;
• receiving a first input data element corresponding to the first row-oriented bus and a second input data element corresponding to the second row-oriented bus;
• at a processing element of the row and a first column of the systolic array:
• performing a set of operations on the first weight and the first input data element, and
• providing the first weight and the first input data element to a processing element of a third column of the systolic array, wherein the first column and the third column are separated by at least a second column of the systolic array;
• and
• at a processing element of the row and the second column of the systolic array:
• performing the set of operations on the second weight and the second input data element, and
• providing the second weight and the second input data element to a processing element of a fourth column of the systolic array, wherein the second column and the fourth column are separated by at least the third column of the systolic array.