State machine block for high-level synthesis

A state machine block that implements a control path of a finite state machine comprising:

• a state register storing a current state value;
• an input sequence encoder that receives one or more external input signals and said current state value and generates one or more encoded sequence signals;
• a memory unit that receives said one or more encoded sequence signals and at least a portion of said current state value and generates a memory unit next state value and one or more state control signals;
• an accumulator unit that receives one or more of said state control signals and said current state value and is configured to perform an arithmetic operation on said current state value to generate an accumulator unit next state value;
• and
• a control unit that receives said memory unit next state value and said accumulator unit next state value and one or more of said state control signals and wherein said control unit determines a next state of the finite state machine based on either the accumulator next state value or the memory unit next state value,
• wherein said memory unit determines a next state for the finite state machine when said current state value represents a state that is not within a branch-free path of the finite state machine.

A state machine block that implements a control path of a finite state machine comprising:

• a state register storing a current state value;
• an input sequence encoder that receives one or more external input signals and said current state value and generates one or more encoded sequence signals;
• a memory unit that receives said one or more encoded sequence signals and at least a portion of said current state value and generates a memory unit next state value and one or more state control signals;
• an accumulator unit that receives one or more of said state control signals and said current state value and is configured to perform an arithmetic operation on said current state value to generate an accumulator unit next state value;
• and
• a control unit that receives said memory unit next state value and said accumulator unit next state value and one or more of said state control signals and wherein said control unit determines a next state of the finite state machine based on either the accumulator next state value or the memory unit next state value,
• wherein said accumulator unit comprises an adder configured such that an increment by one is performed on said current state value to produce said accumulator unit next state value.

A state machine block that implements a control path of a finite state machine comprising:

• a state register storing a current state value;
• an input sequence encoder that receives one or more external input signals and said current state value and generates one or more encoded sequence signals;
• a memory unit that receives said one or more encoded sequence signals and at least a portion of said current state value and generates a memory unit next state value and one or more state control signals;
• an accumulator unit that receives one or more of said state control signals and said current state value and is configured to perform an arithmetic operation on said current state value to generate an accumulator unit next state value;
• and
• a control unit that receives said memory unit next state value and said accumulator unit next state value and one or more of said state control signals and wherein said control unit determines a next state of the finite state machine based on either the accumulator next state value or the memory unit next state value,
• wherein said accumulator unit comprises one or more registers that store one or more of said state control signals.

A state machine block that implements a control path of a finite state machine comprising:

• a state register storing a current state value;
• an input sequence encoder that receives one or more external input signals and said current state value and generates one or more encoded sequence signals;
• a memory unit that receives said one or more encoded sequence signals and at least a portion of said current state value and generates a memory unit next state value and one or more state control signals;
• an accumulator unit that receives one or more of said state control signals and said current state value and is configured to perform an arithmetic operation on said current state value to generate an accumulator unit next state value;
• and
• a control unit that receives said memory unit next state value and said accumulator unit next state value and one or more of said state control signals and wherein said control unit determines a next state of the finite state machine based on either the accumulator next state value or the memory unit next state value,
• wherein said control unit comprises a multiplexor that selects between said accumulator next state value and said memory unit next state value based on one or more of said state control signals.

A state machine block that implements a control path of a finite state machine comprising:

• a state register storing a current state value;
• an input sequence encoder that receives one or more external input signals and said current state value and generates one or more encoded sequence signals;
• a memory unit that receives said one or more encoded sequence signals and at least a portion of said current state value and generates a memory unit next state value and one or more state control signals;
• an accumulator unit that receives one or more of said state control signals and said current state value and is configured to perform an arithmetic operation on said current state value to generate an accumulator unit next state value;
• and
• a control unit that receives said memory unit next state value and said accumulator unit next state value and one or more of said state control signals and wherein said control unit determines a next state of the finite state machine based on either the accumulator next state value or the memory unit next state value,
• wherein said memory unit receives a proper subset of the bits of said current state value.

A state machine block that implements a control path of a finite state machine comprising:

• a state register storing a current state value;
• an input sequence encoder that receives one or more external input signals and said current state value and generates one or more encoded sequence signals;
• a memory unit that receives said one or more encoded sequence signals and at least a portion of said current state value and generates a memory unit next state value and one or more state control signals;
• an accumulator unit that receives one or more of said state control signals and said current state value and is configured to perform an arithmetic operation on said current state value to generate an accumulator unit next state value;
• a control unit that receives said memory unit next state value and said accumulator unit next state value and one or more of said state control signals and wherein said control unit determines a next state of the finite state machine based on either the accumulator next state value or the memory unit next state value;
• and
• a state decoder that receives said current state value and generates output signals.

A state machine block that implements a control path of a finite state machine comprising:

• a state register storing a current state value;
• an input sequence encoder that receives one or more external input signals and said current state value and generates one or more encoded sequence signals;
• a memory unit that receives said one or more encoded sequence signals and at least a portion of said current state value and generates a memory unit next state value and one or more state control signals;
• an accumulator unit that receives one or more of said state control signals and said current state value and is configured to perform an arithmetic operation on said current state value to generate an accumulator unit next state value;
• and
• a control unit that receives said memory unit next state value and said accumulator unit next state value and one or more of said state control signals and wherein said control unit determines a next state of the finite state machine based on either the accumulator next state value or the memory unit next state value,
• wherein one or more of the set consisting of said input sequence encoder, said memory unit, said arithmetic unit and said control unit is implemented within a specialized hard block within a field programmable gate array (FPGA).

A state machine block that implements a control path of a finite state machine comprising:

• a state register storing a current state value;
• an input sequence encoder that receives one or more external input signals and said current state value and generates one or more encoded sequence signals;
• a memory unit that receives said one or more encoded sequence signals and at least a portion of said current state value and generates a memory unit next state value and one or more state control signals;
• an accumulator unit that receives one or more of said state control signals and said current state value and is configured to perform an arithmetic operation on said current state value to generate an accumulator unit next state value;
• and
• a control unit that receives said memory unit next state value and said accumulator unit next state value and one or more of said state control signals and wherein said control unit determines a next state of the finite state machine based on either the accumulator next state value or the memory unit next state value,
• wherein said memory unit, said arithmetic unit and said control unit are all implemented within a specialized hard block within a field programmable gate array (FPGA).

A state machine block that implements a control path of a finite state machine comprising:

• a state register storing a current state value;
• an input sequence encoder that receives one or more external input signals and said current state value and generates one or more encoded sequence signals;
• a memory unit that receives said one or more encoded sequence signals and at least a portion of said current state value and generates a memory unit next state value and one or more state control signals;
• an accumulator unit that receives one or more of said state control signals and said current state value and is configured to perform an arithmetic operation on said current state value to generate an accumulator unit next state value;
• and
• a control unit that receives said memory unit next state value and said accumulator unit next state value and one or more of said state control signals and wherein said control unit determines a next state of the finite state machine based on either the accumulator next state value or the memory unit next state value,
• wherein one or more of the set consisting of said input sequence encoder, said memory unit, said arithmetic unit and said control unit is implemented using a hardware accelerator.

A state machine block that implements a control path of a finite state machine comprising:

• a state register storing a current state value;
• an input sequence encoder that receives one or more external input signals and said current state value and generates one or more encoded sequence signals;
• a memory unit that receives said one or more encoded sequence signals and at least a portion of said current state value and generates a memory unit next state value and one or more state control signals;
• an accumulator unit that receives one or more of said state control signals and said current state value and is configured to perform an arithmetic operation on said current state value to generate an accumulator unit next state value;
• and
• a control unit that receives said memory unit next state value and said accumulator unit next state value and one or more of said state control signals and wherein said control unit determines a next state of the finite state machine based on either the accumulator next state value or the memory unit next state value,
• wherein one or more of the set consisting of said input sequence encoder, said memory unit, said arithmetic unit and said control unit is implemented using soft logic as part of a field programmable gate array (FPGA).