Memory rank design for a memory channel that is optimized for graph applications

A computing system, comprising:

• a plurality of CPU processing cores;
• a graphics processing unit;
• a memory controller, a memory channel emanating from the memory controller, the memory channel characterized as having eight transfers of eight bits of raw data per burst access, a memory module coupled to the memory channel, the memory module comprising a rank of memory chips, the rank of memory chips comprising first, second and third X4 memory chips, the X4 memory chips conforming to a JEDEC dual data rate (DDR) memory interface specification, the first and second X4 memory chips to couple to an eight bit raw data portion of the memory channel's data bus, the third X4 memory chip to couple to an error correction coding (ECC) information portion of the memory channel's data bus.

A memory controller, comprising:

• an interface to communicate with a memory chip that conforms to a JEDEC dual data rate (DDR) memory interface specification, the memory controller comprising logic circuitry to:
• access memory chips that conform to the JEDEC DDR interface specification with eight transfers of eight bits of raw data and four bits of ECC information per burst access;
• calculate ECC information from a burst access's raw data with a symbol orientation that is based on a manufacturer of the memory chips.