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US 11,307,999 B2Granted
Data cache segregation for spectre mitigation
AssigneeSony Interactive Entertainment Inc.
InventorPaul T. Robinson
Life of this patent
Estimating the term…
Abstract
The data cache of a processor is segregated by execution mode, eliminating the danger of certain malware by no longer sharing the resource. Kernel-mode software can adjust the relative size of the two portions of the data cache, to dynamically accommodate the data-cache needs of varying workloads.
Claims20
A device comprising:
- at least one central processing unit (CPU) assembly comprising:
- at least a first CPU thread;
- at least a first cache accessible to the first CPU thread;
- plural signal lines for communicating data between the first CPU thread and the first cache, the CPU thread being configured to expose a value on at least a first signal line of the plural signal lines, a first value on the first signal line indicating a memory address associated with first mode cache, a second value on the first signal line indicating a memory address associated with second mode cache, wherein data associated with a second mode application can be written to and read from second mode cache such that no second mode application can detect operations of the first mode cache.
1 more element
An apparatus comprising:
- at least one central processing unit (CPU) core comprising:
- at least a first CPU thread;
- cache assembly accessible to the first CPU thread;
- and
- plural signal lines for communicating data between the first CPU thread and the cache assembly, the CPU thread being configured to expose a value on at least a first signal line of the plural signal lines, a first value on the first signal line indicating a memory address associated with a first mode cache of the cache assembly, a second value on the first signal line indicating a memory address associated with a second mode cache of the cache assembly.
2 more elements
A method, comprising:
- segregating data cache of a processor according to execution mode, execution mode comprising first mode and second mode;
- and
- exposing a value on at least a first signal line of plural signal lines, a first value on the first signal line indicating a memory address associated with the first mode, a second value on the first signal line indicating a memory address associated with the second mode.
Dependencies are inferred from the claim text.