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US 11,307,988 B2Granted
Configurable cache for multi-endpoint heterogeneous coherent system
AssigneeTexas Instruments Incorporated
InventorsKai Chirca, Matthew David Pierson
Life of this patent
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Abstract
A device includes a memory bank. The memory bank includes data portions of a first way group. The data portions of the first way group include a data portion of a first way of the first way group and a data portion of a second way of the first way group. The memory bank further includes data portions of a second way group. The device further includes a configuration register and a controller configured to individually allocate, based on one or more settings in the configuration register, the first way and the second way to one of an addressable memory space and a data cache.
Claims20
A device comprising:
- a memory bank including:
- data portions of a first way group including:
- a data portion of a first way of the first way group;
- and
- a data portion of a second way of the first way group;
- and
- data portions of a second way group;
- a configuration register;
- and
- a controller configured to determine:
- a first way identifier for the first way based on a first randomly generated allocation pointer, a first AND mask, and a first OR mask;
- a second way identifier for the second way based on the first randomly generated allocation pointer, a second AND mask, and a second OR mask;
- a first group identifier for the first way group based on a set of most significant bits of the first randomly generated allocation pointer;
- and
- a second group identifier for the second way group based on a set of most significant bits of a second randomly generated allocation pointer;
- wherein the controller is configured to individually allocate, based on one or more settings in the configuration register, the first way and the second way to one of an addressable memory space and a data cache.
13 more elements
A system comprising:
- multi-core shared memory controller (MSMC) including:
- a processor interface;
- an external memory interface;
- a memory bank including:
- data portions of a first way group including:
- a data portion of a first way of the first way group;
- and
- a data portion of a second way of the first way group;
- and
- data portions of a second way group;
- a configuration register;
- and
- a controller configured to determine:
- a first way identifier for the first way based on a first randomly generated allocation pointer, a first AND mask, and a first OR mask;
- a second way identifier for the second way based on the first randomly generated allocation pointer, a second AND mask, and a second OR mask;
- a first group identifier for the first way group based on a set of most significant bits of the first randomly generated allocation pointer;
- and
- a second group identifier for the second way group based on a set of most significant bits of a second randomly generated allocation pointer;
- wherein the controller is configured to individually allocate, based on one or more settings in the configuration register, the first way and the second way to one of an addressable memory space and a data cache;
- a processor package connected to the processor interface;
- and
- an external memory device connected to the external memory interface.
19 more elements
A method comprising:
- receiving, at a controller of a multi-core shared memory controller (MSMC), a configuration setting, the MSMC including a memory bank including:
- data portions of a first way group including:
- a data portion of a first way of the first way group;
- and
- a data portion of a second way of the first way group;
- and
- data portions of a second way group;
- and
- determining, by the controller, a first way identifier for the first way based on a first randomly generated allocation pointer, a first AND mask, and a first OR mask, a second way identifier for the second way based on the first randomly generated allocation pointer, a second AND mask, and a second OR mask, a first group identifier for the first way group based on a set of most significant bits of the first randomly generated allocation pointer, and a second group identifier for the second way group based on a set of most significant bits of a second randomly generated allocation pointer;
- allocating, at the controller, the first way and the second way to one of an addressable memory space and a data cache based on the configuration setting.
7 more elements
Dependencies are inferred from the claim text.