Technologies for direct matrix read and write operations

A compute device comprising:

• a data storage device having a memory including a plurality of bit-addressable memory units and a data storage controller to:
• receive a memory access request from a processor to perform a read or write operation on matrix data stored in one or more of the plurality of memory units, the memory access request to indicate a start address of the matrix data;
• determine, with decoder circuitry, whether the matrix data is stored in row-major or column-major format based on a matrix descriptor;
• determine, with the decoder circuitry, whether to perform a row-major memory read or write operation or a column-major memory read or write operation based on whether the matrix data is stored in row-major or column-major format and based on a row-major or a column-major flag in the memory access request that is indicative of whether to perform a row-major or a column-major readout of the matrix data;
• in response to a determination to perform a row-major memory read or write operation, perform the read or write operation along memory rows specified by the memory access request;
• and
• in response to a determination to perform a column-major memory read or write operation, perform the read or write operation along memory columns specified by the memory access request.

A method comprising:

• receiving a memory access request from a processor to perform a read or write operation on matrix data stored in one or more of a plurality of bit-addressable memory units, the memory access request to indicate a start address of the matrix data;
• determining, with decoder circuitry, whether the matrix data is stored in row-major or column-major format based on a matrix descriptor;
• determining, with the decoder circuitry, whether to perform a row-major memory read or write operation or a column-major memory read or write operation based on whether the matrix data is stored in row-major or column-major format and based on a row-major or a column-major flag in the memory access request that is indicative of whether to perform a row-major or a column-major readout of the matrix data;
• in response to a determination to perform a row-major memory read or write operation, perform the read or write operation along memory rows specified by the memory access request;
• and
• in response to a determination to perform a column-major memory read or write operation, perform the read or write operation along memory columns specified by the memory access request.