Memory device with configurable performance and defectivity management

A method of operating a memory device, the method comprising:

• receiving memory access requests to a memory array of the memory device from a host device;
• accessing the memory array of the memory device according to a first memory management protocol, the first memory management protocol including boundary conditions for multiple operating conditions comprising program/erase (P/E) cycles, error management operations, drive writes per day (DWPD), and power consumption;
• monitoring operating conditions of the memory array for the P/E cycles, error management operations, DWPD, power consumption, and a level of memory cell defectivity;
• determining when a boundary condition for one of the multiple operating conditions is met;
• and
• changing, in response to determining that a first boundary condition for a first monitored operating condition is met, one or more operating conditions of the first memory management protocol to establish a second memory management protocol for the memory access operations, the second memory management protocol including a changed boundary condition of a second monitored operating condition;
• and
• changing one or both of a number of parity bits stored in the memory array and an amount of duplicated data stored in the memory array according to a determined level of memory cell defectivity.

A system comprising:

• a host device;
• and
• a memory device, the memory device including:
• a memory array including memory cells;
• an interface configured to receive memory access requests from the host device;
• a memory control unit operatively coupled to the memory array and the interface, the memory control unit comprising a processor configured to execute instructions stored on the memory device that, when executed by the processor, cause the processor to:
• control operation of the memory array according to a first memory management protocol for memory access operations, the first memory management protocol including a memory cell defectivity protocol and boundary conditions for multiple operating conditions comprising program/erase (P/E) cycles, error management operations, drive writes per day (DWPD), and power consumption;
• monitor operating conditions of the memory array for the P/E cycles, error management operations, DWPD, power consumption, and memory cell endurance;
• determine when a boundary condition for one of the multiple operating conditions is met;
• in response to determining that a first boundary condition for a first monitored operating condition is met, change one or more operating conditions of the first memory management protocol to establish a second memory management protocol for the memory access operations, the second memory management protocol including a changed boundary condition of a second monitored operating condition;
• and establish the second memory management protocol by changing one or more of a number of memory cells subject to error detection for a memory access request, a number of parity bits stored for the memory access request, and an amount of duplicated data written as part of the memory access request according to a determined operating condition of the memory array for memory cell endurance.