US 11,307,941 B1 · System and method for hybrid kernel- and user-space incremental and full checkpointing

Abstract

A system includes a multi-process application that runs. A multi-process application runs on primary hosts and is checkpointed by a checkpointer comprised of at least one of a kernel-mode checkpointer module and one or more user-space interceptors providing at least one of barrier synchronization, checkpointing thread, resource flushing, and an application virtualization space. Checkpoints may be written to storage and the application restored from said stored checkpoint at a later time. Checkpointing may be incremental using Page Table Entry (PTE) pages and Virtual Memory Areas (VMA) information. Checkpointing is transparent to the application and requires no modification to the application, operating system, networking stack or libraries. In an alternate embodiment the kernel-mode checkpointer is built into the kernel.

Claims20

Dependent claims

A system, comprising:

one or more Central Processing Units (CPUs) operatively connected to computer system memory and configured to execute one or more multi-process applications on a host with a host operating system;
a kernel-space checkpointer configured to provide incremental kernel-space checkpointing of the multi-process applications;
and
one or more user-space interceptors preloaded into an address space of each application process, wherein said user-space interceptors comprise a barrier;
wherein said kernel-space checkpointer is called while the execution of application processes are halted at said barrier;
wherein said incremental checkpointing is comprised of tracking dirty pages for page table entry (PTE) pages within the address space of the one or more multi-process applications;
wherein a dirty page bit is repurposed to track dirty pages for incremental checkpointing.

4 more elements

Dependencies are inferred from the claim text.

Facts

Application

16/854,860Filed 21 Apr 2020 · continuation

Priority

28 Apr 2011

Granted

19 Apr 2022

Term ends

Not estimatedThe source records don’t support an estimate.

Classification10 codes

G06F 11/1471
Error detection or correction of the data by redundancy in operations: involving logging of persistent data for recovery
G06F 11/1407
At machine instruction level: checkpointing the instruction stream
G06F 11/1438
At system level: restarting or rejuvenating
G06F 11/1446
Error detection or correction of the data by redundancy in operations: point-in-time backing up or restoration of persistent data

Family

Application13/096,461Parent of this continuation-in-part · filed 28 Apr 2011

Application14/292,156Parent of this continuation · filed 30 May 2014

US 8,745,442 B1Parent of this continuation-in-part · filed 3 Jun 2014

Application15/167,481Parent of this continuation · filed 27 May 2016

US 9,354,977 B1Parent of this continuation · filed 31 May 2016

Application16/031,549Parent of this continuation · filed 10 Jul 2018

US 10,019,327 B1Parent of this continuation · filed 10 Jul 2018

US 10,628,272 B1Parent of this continuation · filed 21 Apr 2020

Application14/292,156Parent of this continuation-in-part

US 11,307,941 B1This patent

From the US filing history. Foreign family members aren’t listed.

System and method for hybrid kernel- and user-space incremental and full checkpointing

Life of this patent

System and method for hybrid kernel- and user-space incremental and full checkpointing

Life of this patent

Abstract

Claims20