Back to results
US 11,307,926 B2Granted
Memory system, operation method of the same, and memory controller
AssigneeSK hynix Inc.
InventorsTae-Pyeong Kim, Jae-Woo Kim, Hyun-Jin Noh, Pyo-Young Han
Life of this patent
Estimating the term…
Abstract
A method for operating a memory system includes: performing a first training operation for alignment between a clock and a data strobe signal; performing a second training operation for alignment between the data strobe signal and the data; detecting an error of the second training operation; and adjusting a delay value of the data strobe signal in response to the detection of the error.
Claims13
A method for operating a memory system, comprising:
- performing a first training operation for alignment between a clock and a data strobe signal;
- performing a second training operation for alignment between the data strobe signal and data;
- detecting an error of the second training operation;
- and
- adjusting a delay value of the data strobe signal for the first training operation in response to the detection of the error.
2 more elements
A memory controller, comprising:
- a clock transfer circuit suitable for transferring a clock;
- a data strobe signal transfer circuit suitable for transferring a data strobe signal;
- a data strobe signal delay circuit suitable for delaying a preliminary data strobe signal by a first delay value to generate the data strobe signal;
- a data receiving circuit;
- a data transfer circuit suitable for transferring data;
- a data delay circuit suitable for delaying a preliminary data by a second delay value to generate the data;
- a first training control circuit suitable for adjusting the first delay value in response to a signal received by the data receiving circuit during a first training operation for alignment between the clock and the data strobe signal;
- and
- a second training control circuit for adjusting the second delay value in response to a signal received by the data receiving circuit during a second training operation for alignment between the data strobe signal and the data,
- wherein, when the second training control circuit detects an error of the second training operation, the second training control circuit adjusts the first delay value.
7 more elements
A memory system, comprising:
- a memory controller suitable for adjusting a first delay value for a data strobe signal in response to a sampling result for alignment between a clock and the data strobe signal during a first training operation, adjusting a second delay value for data in response to feedback data for alignment between the data strobe signal and the data during a second training operation which is performed after the first training operation, and when an error of the second training operation is detected, adjusting the first delay value and then performing the first training operation and the second training operation again;
- and
- a memory suitable for sampling the clock received from the memory controller based on the data strobe signal received from the memory controller to produce a sampling result during the first training operation and transferring the sampling result to the memory controller, receiving the data from the memory controller based on the data strobe signal received from the memory controller during the second training operation, and transferring the received data to the memory controller as the feedback data.
Dependencies are inferred from the claim text.