Fail information control circuit, semiconductor apparatus including the same, and fail information control method of semiconductor apparatus

A fail information control circuit comprising:

• a comparison circuit configured to generate a comparison result signal by comparing read data and write data;
• a fail bit discrimination circuit configured to generate a first fail discrimination signal for discriminating a fail detected when the write data has a first value and a second fail discrimination signal for discriminating a fail detected when the write data has a second value, in response to the comparison result signal;
• and
• a fail information output circuit configured to:
• generate a first counting signal and a second counting signal by counting the first fail discrimination signal and the second fail discrimination signal;
• and
• generate a first counting correction signal and a second counting correction signal by resetting remaining bits, except for a most significant bit of a first level among bits of the first counting signal and the second counting signal.

A semiconductor apparatus comprising:

• a memory area;
• input/output pads;
• and
• a fail information control circuit configured to:
• generate a first fail discrimination signal when a fail detected where the write data has a value ‘0’ and generate a second fail discrimination signal when a fail detected where the write data has a value ‘1’ according to a result of comparing the write data provided to the memory area with read data outputted from the memory area;
• and
• generate a first counting signal by counting the first fail discrimination signal and generate a second counting signal by counting the second fail discrimination signal,
• wherein the first counting signal and the second counting signal are outputted to an exterior through the input/output pads.

A fail information control method of a semiconductor apparatus, the method comprising:

• a comparison step of comparing read data and write data;
• a counting step of classifying a type of fail bits into a first fail when the write data and the read data do not coincide with each other in the comparison step, and generating a first counting signal;
• a counting step of classifying a type of fail bits into a first fail and a second fail when the write data and the read data do not coincide with each other in the comparison step, and generating a first counting signal and a second counting signal;
• and
• an output step of outputting the first counting signal and the second counting signal to an exterior of the semiconductor apparatus,
• wherein the counting step comprises:
• determining whether the write data is ‘0’ when the write data and the read data do not coincide with each other;
• and
• increasing a value of the first counting signal when the write data is determined to be ‘0’ and increasing a value of the second counting signal when the write data is determined not to be ‘0’.