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US 11,307,861 B2Granted
Securing conditional speculative instruction execution
AssigneeMicron Technology, Inc.
InventorSteven Jeffrey Wallach
Life of this patent
Estimating the term…
Abstract
A method performed in a processor, includes: receiving, in the processor, a branch instruction in the processing; determining, by the processor, an address of an instruction after the branch instruction as a candidate for speculative execution, the address including an object identification and an offset; and determining, by the processor, whether or not to perform speculative execution of the instruction after the branch instruction based on the object identification of the address.
Claims20
A method comprising:
- determining, by a processor, a memory address associated with an instruction for execution after a branch instruction, the memory address including an object identification and an offset;
- and
- determining, by the processor, whether to execute the instruction after the branch instruction based on the object identification of the memory address.
A processor, comprising:
- a register of a first predetermined width, the register having:
- an object identification portion of a second predetermined width;
- and
- an offset portion;
- and
- an execution unit configured to execute an instruction using a memory address stored in the register;
- wherein the processor is configured to determine whether or not to execute the instruction based on an object identification of the memory address stored in the object identification portion of the register.
4 more elements
A computer system, comprising:
- a memory storing a set of instructions and a set of data items;
- and
- a processor configured to load the instructions for execution according to memory addresses and execute the instructions to operate on the data items identified using memory addresses;
- wherein a second instruction is to be executed after a first instruction;
- and
- wherein the processor is configured to determine whether to execute the second instruction based on an object identification of a memory address associated with the second instruction.
3 more elements
Dependencies are inferred from the claim text.