Iterating group sum of multiple accumulate operations

A system comprising:

• a scheduler operative to schedule a single instruction, multiple data (SIMD) thread;
• one or more processors operative to execute the SIMD thread;
• and
• logic encoded in one or more non-transitory computer-readable storage media for execution by the one or more processors and when executed operative to cause the one or more processors to perform operations comprising:
• initiating, by the scheduler, the SIMD thread;
• fetching, by the one or more processors, a plurality of instructions for the SIMD thread from a memory;
• determining, by a thread arbiter of the processor, at least one instruction of the plurality of instructions that is a walk instruction block, wherein the walk instruction block includes a walk-endwalk pair of instructions, wherein the walk instruction block includes a GSOMAC (Group Sum of Multiply Accumulate) instruction;
• iterating a block of instructions within the walk-endwalk pair of instructions of the walk instruction block for a subset of channels of the SIMD thread, wherein the walk-endwalk instructions are responsible for iterating the block of instructions when a size of the SIMD thread is greater than a maximum native SIMD instruction width, and an execution mask is responsible for iterating the block of instructions when the size of the SIMD thread is less than the maximum native SIMD instruction width, wherein the walk instruction block includes a walk size, and wherein the walk size is a number of channels in the subset of channels of the SIMD thread that are processed in the iterating in association with the walk instruction block;
• providing, by the thread arbiter, the walk instruction block to a code block iterator;
• and
• executing, by the thread arbiter, the walk instruction block based on the walk size.