Branch target variant of branch-with-link instruction

A data processing method comprising:

• in response to a branch instruction, triggering a non-sequential change of program flow to an instruction at a target address;
• when the non-sequential change of program flow is triggered in response to a branch-with-link instruction, setting a return address for a subsequent return of program flow;
• and
• when the non-sequential change of program flow is triggered in response to at least one target-checking type of branch instruction, checking whether the instruction at the target address is at least one permitted type of branch target instruction, and triggering an error handling response in response to determining that the instruction at the target address is an instruction other than the at least one permitted type of branch target instruction;
• wherein for at least a subset of said at least one target-checking type of branch instruction, said at least one permitted type of branch target instruction includes a branch target variant of the branch-with-link instruction.

A non-transitory storage medium storing a computer program for controlling a host data processing apparatus to provide an instruction execution environment for execution of instructions of target program code, comprising:

• instruction decode program logic to decode instructions of the target program code;
• and
• processing program logic to perform data processing in response to instructions decoded by the instruction decode program logic;
• in which:
• in response to a branch instruction, the instruction decode program logic is configured to control the processing program logic to trigger a non-sequential change of program flow to an instruction at a target address;
• when the non-sequential change of program flow is triggered in response to a branch-with-link instruction, the instruction decode program logic is configured to control the processing program logic to set a return address for a subsequent return of program flow;
• when the non-sequential change of program flow is triggered in response to at least one target-checking type of branch instruction, the instruction decode program logic is configured to control the processing program logic to check whether the instruction at the target address is at least one permitted type of branch target instruction, and trigger an error handling response in response to determining that the instruction at the target address is an instruction other than the at least one permitted type of branch target instruction;
• and
• for at least a subset of said at least one target-checking type of branch instruction, said at least one permitted type of branch target instruction includes a branch target variant of the branch-with-link instruction.