Register-provided-opcode instruction

A data processing method comprising:

• decoding an instruction specifying an opcode and at least one data operand, to control processing circuitry to perform a data processing operation identified by the opcode on the at least one data operand, to generate a result value to be written to a destination register;
• and
• when the decoded instruction is a register-provided-opcode instruction specifying at least one source register:
• at least part of the opcode is a register-provided opcode represented by a first portion of data stored in the at least one source register of the register-provided-opcode instruction;
• the at least one data operand comprises data represented by a second portion of the data stored in the at least one source register;
• in response to the register-provided-opcode instruction, the processing circuitry selects, based on at least the register-provided opcode, one of a plurality of different data processing operations supported for the same instruction encoding of the register-provided-opcode instruction;
• and
• said plurality of different data processing operations include at least two different data processing operations which are each capable, for at least a subset of possible input values for said at least one data operand, of generating the result value with a different value or a different data format to said at least one data operand.

A non-transitory, computer-readable storage medium storing a computer program, which when executed by a host data processing apparatus, causes the host data processing apparatus to simulate processing of a target program by target processing circuitry, the computer program comprising:

• register emulating program logic to maintain a register emulating data structure emulating a plurality of registers of the target processing circuitry;
• and
• instruction decoding program logic to decode an instruction of the target program specifying an opcode and at least one data operand, to control the host data processing apparatus to perform a data processing operation identified by the opcode on the at least one data operand, to generate a result value to be written to part of the register emulating data structure corresponding to a destination register of said plurality of registers;
• in which for a register-provided-opcode instruction specifying at least one source register:
• at least part of the opcode is a register-provided opcode represented by a first portion of data corresponding to the at least one source register of the register-provided-opcode instruction;
• the at least one data operand comprises data represented by a second portion of the data corresponding to the at least one source register;
• in response to the register-provided-opcode instruction, the instruction decoding program logic is configured to control the host data processing apparatus to select, based on at least the register-provided opcode, one of a plurality of different data processing operations supported for the same instruction encoding of the register-provided-opcode instruction;
• and
• said plurality of different data processing operations include at least two different data processing operations which are each capable, for at least a subset of possible input values for said at least one data operand, of generating the result value with a different value or a different data format to said at least one data operand.