Memory write log storage processors, methods, systems, and instructions
AssigneeIntel Corporation
InventorsKshitij Doshi, Roman Dementiev, Vadim Sukhomlinov
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AssigneeIntel Corporation
InventorsKshitij Doshi, Roman Dementiev, Vadim Sukhomlinov
Estimating the term…
A processor of an aspect includes a decode unit to decode an instruction. The instruction is to indicate a destination memory address information. An execution unit is coupled with the decode unit. The execution unit, in response to the decode of the instruction, is to store memory addresses, for at least all initial writes to corresponding data items, which are to occur after the instruction in original program order, to a memory address log. A start of the memory address log is to correspond to the destination memory address information. Other processors, methods, systems, and instructions are also disclosed.
A processor comprising:
A method performed by a processor comprising:
A system to process instructions comprising:
An article of manufacture comprising a non-transitory machine-readable storage medium, the non-transitory machine-readable storage medium storing a plurality of instructions including an instruction that is to indicate a destination memory address information corresponding to a start of a memory address log, the instruction, if executed by a machine, is to cause the machine to perform operations comprising to:
Dependencies are inferred from the claim text.