Managing threshold voltage drift based on operating characteristics of a memory sub-system

A non-transitory computer readable medium comprising instructions, which when executed by a processing device, cause the processing device to perform operations comprising:

• establishing a plurality of sets of values corresponding to a plurality of operating characteristics of a memory sub-system, wherein the plurality of operating characteristics comprises two or more of a write-to-write delay time, a write-to-read delay time, a memory die temperature or a cycling condition;
• for each of the plurality of sets of values corresponding to the plurality of operating characteristics, identifying a target read voltage level corresponding to a decreased bit error rate of a programming distribution of the memory sub-system;
• storing a table including the target read voltage level corresponding to each set of values of the plurality of sets of values corresponding to the plurality of operating characteristics;
• in response to a read command associated with a memory cell, measuring a current set of measured values of the plurality of operating characteristics associated with a memory cell;
• performing a comparison of the current set of measured values and the set of values associated with the plurality of operating characteristics stored in the table to identify a match between a first set of values of the plurality of sets of values corresponding to the plurality of operating characteristics and the current set of measured values;
• identifying, using the table, a first stored target read voltage level corresponding to the first set of values corresponding to the plurality of operating characteristics matching the current set of measured values;
• and
• executing, by a processing device, the read command using the first stored target read voltage level corresponding to the first set of values of the plurality of sets of values.

A system comprising:

• a memory component;
• and
• a processing device, operatively coupled with the memory component, to:
• establish a plurality of sets of values corresponding to a plurality of operating characteristics of a memory sub-system, wherein the plurality of operating characteristics comprises two or more of a write-to-write delay time, a write-to-read delay time, a memory die temperature or a cycling condition;
• for each of the plurality of sets of values corresponding to the plurality of operating characteristics, identify a target read voltage level corresponding to a decreased bit error rate of a programming distribution of the memory sub-system;
• store a data structure including the target read voltage level corresponding to each set of values of the plurality of sets of values corresponding to the plurality of operating characteristics;
• in response to a read command associated with a memory cell, measure a current set of measured values of the plurality of operating characteristics associated with a memory cell;
• identify a match between a first set of values corresponding to the plurality of operating characteristics stored in the data structure and the current set of measured values;
• performing a comparison of the current set of values and the set of values associated with the plurality of operating characteristics stored in the data structure to identify a match between a first set of values of the plurality of sets of values corresponding to the plurality of operating characteristics and the current set of measured values;
• and
• execute the read command using a first stored target read voltage level corresponding to the first set of values of the plurality of sets of values.