Memory controller, and method thereof

Abstract

A memory controller according to an aspect of the present invention includes a buffer configured to store an operation command table including operation commands entered by a user, a BIST (built-in self-tester) controller configured to generate a pointer pointing to an operation command, a command and address generator configured to decode the operation command corresponding to the pointer among the operation commands to generate first memory commands, a command and address queue comprising queues for storing the first memory commands, and a command requester configured to output a test command including first operation command information for the generation of a memory command output from a first queue included in the queues among the memory command, location information of the first queue, and the operation commands.

Dependencies are inferred from the claim text.