US 11,307,767 B1Granted

System for controlling memory operations in system-on-chips

AssigneeNXP USA, Inc.

InventorsNidhi Sinha, Dinesh Joshi, Akshay Kumar Pathak

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Abstract

A system-on-chip (SoC) includes a system memory, a memory controller, and a memory management system coupled therebetween. The memory management system is configured to receive, from the memory controller, a first control signal that is indicative of a memory operation associated with the system memory, and output and provide a second control signal to the system memory to control an execution of the memory operation. The second control signal is outputted such that when the memory operation corresponds to a first read operation, the first read operation is executed with the system memory, and when the memory operation corresponds to a first write operation, a second read operation is executed with the system memory followed by the first write operation. Thus, the memory management system prevents memory corruption of the system memory when an asynchronous reset event is detected in the SoC.

Claims20

Dependent claims

A memory management system coupled between a memory controller and a system memory for controlling a memory operation associated with the system memory, the memory management system comprising:

a first flip-flop (FF) that is coupled with the memory controller, and configured to receive a first control signal indicative of the memory operation, a power-on reset signal, and a first clock signal, and output a second control signal;
a second FF that is coupled with the memory controller, and configured to receive the first control signal, the power-on reset signal, and a second clock signal, and output a third control signal;
and
a logic gate that is coupled with the first and second FFs and the system memory, and configured to receive the second and third control signals, and output and provide a fourth control signal to the system memory to control an execution of the memory operation, wherein the fourth control signal is outputted such that when the memory operation corresponds to a first read operation, the first read operation is executed with the system memory, and when the memory operation corresponds to a first write operation, a second read operation is executed with the system memory followed by the first write operation.

1 more element

A system-on-chip (SoC), comprising:

a system memory;
a memory controller;
and
a memory management system that is coupled between the memory controller and the system memory, and configured to control a memory operation associated with the system memory, the memory management system comprising:
a first flip-flop (FF) that is coupled with the memory controller, and configured to receive a first control signal indicative of the memory operation, a power-on reset signal, and a first clock signal, and output a second control signal;
a second FF that is coupled with the memory controller, and configured to receive the first control signal, the power-on reset signal, and a second clock signal, and output a third control signal;
and
a logic gate that is coupled with the first and second FFs and the system memory, and configured to receive the second and third control signals, and output and provide a fourth control signal to the system memory to control an execution of the memory operation, wherein the fourth control signal is outputted such that when the memory operation corresponds to a first read operation, the first read operation is executed with the system memory, and when the memory operation corresponds to a first write operation, a second read operation is executed with the system memory followed by the first write operation.

5 more elements

Dependencies are inferred from the claim text.

Facts

Application: 17/071,892Filed 15 Oct 2020
Published: US 2022/0121360 A121 Apr 2022
Granted: 19 Apr 2022
Term ends: Not estimatedThe source records don’t support an estimate.

Classification9 codes

G06F 3/0604
Specifically adapted to achieve a particular effect: improving or facilitating administration, e.g. storage management
G11C 7/1087
Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits: data input latches
G06F 3/0659
Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices: command handling…
G06F 3/0673
In-line storage system: single storage device

Family

US 2022/0121360 A1Published application
US 11,307,767 B1This patent

From the US filing history. Foreign family members aren’t listed.

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