Securely providing multiple wake-up time options for PCI Express

A system comprising:

• a host computer, including,
• a System on a Chip (SoC) processor having a memory controller and a Peripheral Component Interconnect Express (PCIe) root controller including at least one PCIe root port;
• system memory, operatively coupled to the memory controller;
• and
• instructions, to execute on the SoC processor;
• a PCIe device, including,
• a PCIe port coupled to a PCIe root port via a PCIe link having a L1 PM Substates Control 2 Register including a T_POWER_ON Scale field and a T_POWER_ON Value field;
• a power mode capability table structure containing information mapping each of a plurality of respective power modes to a T_POWER_ON Scale value and a T_POWER_ON Value value;
• and
• embedded logic;
• wherein execution of the instructions on the SoC processor and the embedded logic respectively enable the host computer and the PCIe device to,
• generate, at the host computer, a power mode change request defining a power mode;
• send the power mode change request from the host computer over the PCIe link to the PCIe device;
• extract, at the PCIe device, information identifying the power mode from the power mode change request;
• retrieve a T_POWER_ON Scale value and a T_POWER_ON Value value in the power capability table structure for the power mode that is identified;
• and
• set respective values in the T_POWER_ON Scale field and the T_POWER_ON Value field to the T_POWER_ON Scale value and the T_POWER_ON Value value that are retrieved to change the L1.2 Substate exit time to be used by the PCIe device.

A Peripheral Component Interconnect Express (PCIe) device, comprising:

• a PCIe port configured to implement a PCIe stack including a physical layer, link layer, and transaction layer;
• an L1 PM Substates Control 2 Register including a T_POWER_ON Scale field and a T_POWER_ON Value field;
• and
• embedded logic;
• wherein the PCIe device is configured to be coupled to a host via a PCIe link coupled between the host and the PCIe port, and wherein the embedded logic is configured to,
• receive a power mode change request sent from the host over the PCIe link, the power mode change request including information identifying a power mode;
• extract the information identifying the power mode from the power mode change request;
• retrieve a T_POWER_ON Scale value and a T_POWER_ON Value value in the power capability table structure for the power mode that is identified;
• and
• set respective values in the T_POWER_ON Scale field and the T_POWER_ON Value field to the T_POWER_ON Scale value and the T_POWER_ON Value value that are retrieved to change the L1.2 Substate exit time to be used by the PCIe device.