Maintaining historical power level metadata for dynamic voltage and frequency scaling of processor instructions

A processor device comprising:

• a processor core;
• a power controller to control voltage and/or frequency of the processor core;
• and
• a power predictor;
• wherein the power predictor is to:
• receive, from the power controller, a processor core power quantifier that corresponds to a voltage or frequency of the processor core while executing a processor instruction;
• store, based on the processor core power quantifier, an instruction power level in association with the processor instruction;
• subsequently determine that the processor instruction is to be executed by the processor core at a future point in time;
• access the instruction power level previously stored in association with the processor instruction;
• and
• prior to the processor instruction being executed by the processor core, communicate, to the power controller, a proposed power level based on the instruction power level.

A non-transitory computer-readable storage medium that includes executable instructions to cause a power predictor of a processor device to:

• receive, from a power controller that controls voltage and/or frequency of a processor core, a processor core power quantifier that corresponds to a voltage or frequency of the processor core while executing a processor instruction;
• store, based on the processor core power quantifier, an instruction power level in association with the processor instruction;
• subsequently determine that the processor instruction is to be executed by the processor core at a future point in time;
• access the instruction power level previously stored in association with the processor instruction;
• and
• prior to the processor instruction being executed by the processor core, communicate, to the power controller, a proposed power level based on the instruction power level.