Power disable of memory sub-system

A system comprising:

• power circuitry to power on and off a memory sub-system;
• a power disable circuit coupled to a bus connector of a host system and to the power circuitry;
• and
• a processing device, of the memory sub-system, comprising a timer and operatively coupled to the bus connector, to the power disable circuit, and to a memory device of the memory sub-system, wherein the processing device is to:
• ignore, during initial power up of the memory device, a state of a power disable (PWDIS) signal of the bus connector;
• after the memory device is powered on, monitor the state of the PWDIS signal of the bus connector while the PWDIS signal is at a high voltage level;
• in response to the PWDIS signal transitioning to a low voltage level, initiate the timer;
• and
• in response to the timer satisfying a threshold criterion, enable the power disable circuit with an enablement signal;
• and
• wherein the power disable circuit comprises:
• a first field effect transistor (FET) and a second FET with sources mutually coupled and gates to receive the PWDIS signal, wherein, in response to an asserted input of the PWDIS signal at a second gate of the second FET, a drain of the first FET is left floating;
• a latch circuit to assert an output in response to the enablement signal;
• and
• a third FET coupled to the drain of the first FET and to the output of the latch circuit, wherein in response to assertion of the output of the latch circuit, the third FET is to signal to the power circuitry to cut power to the memory sub-system.

A method comprising:

• operating a system comprising a power disable circuit coupled to a bus connector of a host system and to power circuitry, and a processing device operatively coupled to the bus connector, to the power disable circuit, and to a memory device, wherein operating the system comprises:
• ignoring, during initial power up of the memory device, a state of a power disable (PWDIS) signal of the bus connector;
• after the memory device is powered on, the processing device monitoring the state of the PWDIS signal of the bus connector while the PWDIS signal is at a high voltage level;
• in response to the PWDIS signal transitioning to a low voltage level, determining whether a length of time for which the PWDIS signal has been at the low voltage level satisfies a threshold criterion;
• and
• in response to the length of time for which the PWDIS signal has been at the low voltage level satisfying the threshold criterion, the processing device enabling the power disable circuit with a general purpose input/output signal;
• and
• wherein the power disable circuit comprises a first field effect transistor (FET) and a second FET with sources mutually coupled, a latch circuit, and a third FET coupled to a drain of the first FET and to the memory device and the processing device, wherein operating the system further comprises:
• receiving the PWDIS signal at gates of the first FET and the second FET and at an input of the latch circuit;
• in response to an asserted input of the PWDIS signal at a second gate of the second FET, causing the drain of the first FET to be left floating;
• asserting an output of the latch circuit in response to the general purpose input/output signal;
• and
• signaling, by the third FET in response to the asserting the output of the latch circuit, the power circuitry to cut power to the processing device and the memory device.