Clamp circuit

A system, comprising:

• a reference circuit configured to generate a reference voltage;
• an analog-to-digital converter (ADC);
• a conductive line coupled between the reference circuit and the ADC;
• and
• a clamp circuit coupled to the conductive line, the clamp circuit comprising:
• a first current mirror having a first branch and a second branch, wherein the first current mirror is configured to mirror a current flowing through the first branch of the first current mirror to the second branch of the first current mirror;
• and
• a second current mirror having a first branch and a second branch, wherein the second current mirror is configured to mirror a current flowing through the first branch of the second current mirror to the second branch of the second current mirror;
• wherein the first branch of the first current mirror is coupled in series with the second branch of the second current mirror, and the second branch of the first current mirror is coupled in series with the first branch of the second current mirror;
• and
• wherein the first current mirror comprises:
• a first transistor having a drain, a gate, and a source, wherein the drain of the first transistor is coupled to the gate of the first transistor, and the source of the first transistor is coupled to a ground;
• and
• a second transistor having a drain, a gate, and a source, wherein the gate of the second transistor is coupled to the gate of the first transistor, and the source of the second transistor is coupled to the ground.

A clamp circuit, comprising:

• a first transistor having a drain, a gate, and a source, wherein the drain of the first transistor is coupled to the gate of the first transistor, and the source of the first transistor is coupled to a ground;
• a second transistor having a drain, a gate, and a source, wherein the gate of the second transistor is coupled to the gate of the first transistor, and the source of the second transistor is coupled to the ground;
• a third transistor having a drain, a gate, and a source, wherein the drain of the third transistor is coupled to the drain of the first transistor, and the source of the third transistor is coupled to a conductive line;
• and
• a fourth transistor having a drain, a gate, and a source, wherein the drain of the fourth transistor is coupled to the drain of the second transistor and the gate of the fourth transistor, the source of the fourth transistor is coupled to a voltage line, and the gate of the fourth transistor is coupled to the gate of the third transistor.

A method for clamping a voltage on a conductive line, comprising:

• coupling a first current mirror and a second current mirror into a feedback loop;
• coupling a first branch of the second current mirror to a voltage line;
• coupling a second branch of the second current mirror to the conductive line;
• coupling a first branch of the first current mirror to a ground;
• and
• coupling a second branch of the first current mirror to the ground.