US 11,307,253 B2 · Self-test of an asynchronous circuit

Abstract

An indication of an operating mode of an asynchronous circuit may be received. A determination may be made as to whether the operating mode of the asynchronous circuit corresponds to a self-test of the asynchronous circuit. In response to determining that the operating mode of the asynchronous circuit corresponds to the self-test, a first clock signal may be provided to a first portion of a self-test component in a feedback path of the asynchronous circuit and a second clock signal may be provided to a second portion of the self-test component in the feedback path of the asynchronous circuit. Furthermore, a test value may be generated based on the first clock signal and the second clock signal.

Claims20

Dependent claims

A method comprising:

enabling, by a controller, a feedback component of an asynchronous circuit to perform a first self-test of the asynchronous circuit at a first time;
verifying, by the controller, an integrity of the asynchronous circuit based on the first self-test at the first time;
disabling, by the controller, the feedback component after verifying the integrity of the asynchronous circuit at the first time;
enabling, by the controller, the feedback component of the asynchronous circuit to perform a second self-test of the asynchronous circuit at a second time in response to a condition of the asynchronous circuit;
verifying, by the controller, the integrity of the asynchronous circuit based on the second self-test at the second time;
and
disabling, by the controller, the feedback component after verifying the integrity of the asynchronous circuit at the second time.

4 more elements

Dependencies are inferred from the claim text.

Facts

Application

17/136,198Filed 29 Dec 2020 · continuation

Priority

18 Apr 2017

Published

US 2021/0190862 A124 Jun 2021

Granted

19 Apr 2022

Term ends

Not estimatedThe source records don’t support an estimate.

Classification9 codes

G01R 31/31922
Stimuli generation or application of test patterns to the device under test [DUT]: timing generation or clock distribution
G01R 31/31701
Testing of digital circuits: arrangements for setting the Unit Under Test [UUT] in a test mode
G01R 31/3187
Functional testing: built-in tests
G06F 1/06
Generating or distributing clock signals or signals derived directly therefrom: clock generators producing several clock signals

Family

Application62/486,769Us provisional application · filed 18 Apr 2017

Application15/903,980Parent of this continuation · filed 23 Feb 2018

US 2021/0190862 A1Pre-grant publication · published 24 Jun 2021

US 10,884,058 B2Parent of this continuation

US 2018/0299509 A1Published application

US 11,307,253 B2This patent

From the US filing history. Foreign family members aren’t listed.

Self-test of an asynchronous circuit

Life of this patent

Self-test of an asynchronous circuit

Life of this patent

Abstract

Claims20