US 11,307,251 B1Granted

Circuit and testing circuit thereof

AssigneeShanghai Zhaoxin Semiconductor Co., Ltd.

InventorYunhao Xing

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Abstract

A circuit, including a TAP circuit, a routing circuit, a first test path and a second test path, is provided. A first input terminal and a first output terminal of the routing circuit are respectively coupled to a scan output terminal and a first scan input terminal of the TAP circuit. A first terminal of the first test path is coupled to a second input terminal of the routing circuit. A second terminal of the first test path is coupled to a second output terminal of the routing circuit. A first terminal of the second test path is coupled to a third input terminal of the routing circuit. A second terminal of the second test path is coupled to a third output terminal of the routing circuit. The routing circuit couples the scan output terminal of the TAP circuit to the first scan input terminal of the TAP circuit or the first terminal of the first test path or the first terminal of the second test path.

Claims14

Dependent claims

A circuit, comprising:

a test access port circuit, comprising a first scan input terminal and a scan output terminal;
a routing circuit, comprising a first input terminal, a first output terminal, a second input terminal, a second output terminal, a third input terminal and a third output terminal, wherein said first input terminal and said first output terminal of said routing circuit are respectively coupled to said scan output terminal and said first scan input terminal of said test access port circuit;
a first test path, comprising a first terminal and a second terminal, wherein said first terminal of said first test path is coupled to said second input terminal of said routing circuit, said second terminal of said first test path is coupled to said second output terminal of said routing circuit;
and
a second test path, comprising a first terminal and a second terminal, wherein said first terminal of said second test path is coupled to said third input terminal of said routing circuit, and said second terminal of said second test path is coupled to said third output terminal of said routing circuit,
wherein said routing circuit couples said scan output terminal of said test access port circuit to said first scan input terminal of said test access port circuit or said first terminal of said first test path or said first terminal of said second test path.

3 more elements

A testing circuit of a circuit, comprising:

a test access port circuit, wherein a scan output terminal of said test access port circuit is coupled to a first terminal of a first test path of said circuit, a second terminal of said first test path is coupled to a first terminal of a second test path of said circuit, and a second terminal of said second test path is coupled to a first scan input terminal of said test access port circuit;
and
a clock supply circuit, wherein in a shift operation mode, said clock supply circuit provides a shift clock signal to said first test path and said second test path, and in a capture operation mode, said clock supply circuit provides a first clock signal to said first test path, provides a second clock signal to said second test path.

Dependencies are inferred from the claim text.

Facts

Application: 17/084,660Filed 30 Oct 2020
Priority: CN 202011054658.230 Sep 2020
Published: US 2022/0099740 A131 Mar 2022
Granted: 19 Apr 2022
Term ends: Not estimatedThe source records don’t support an estimate.

Classification7 codes

G01R 31/318552
Using scanning techniques, e.g. LSSD, Boundary Scan, JTAG: clock circuits details
G01R 31/31853
Test of Sequential circuits: test of registers
G01R 31/318536
Using scanning techniques, e.g. LSSD, Boundary Scan, JTAG: scan chain arrangements, e.g. connections, test bus, analog signals
G01R 31/318555
Using scanning techniques, e.g. LSSD, Boundary Scan, JTAG: control logic

Family

US 2022/0099740 A1Published application
US 11,307,251 B1This patent

From the US filing history. Foreign family members aren’t listed.

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