Adaptive voltage scaling methods and systems therefor

A logic gate for an adaptive voltage scaling monitor, the logic gate comprising:

• a first N-type metal-oxide semiconductor (NMOS) component having a number of fingers, each finger including a transistor gate;
• a second NMOS component, coupled to the first NMOS component, having a transistor gate;
• a first P-type metal-oxide semiconductor (PMOS) component having a number of fingers, each finger including a transistor gate;
• a second PMOS component, coupled to the first PMOS component, having a transistor gate;
• a first input directly coupled to the transistor gates of the first NMOS component and the transistor gates of the first PMOS component, the first input configured to provide an input signal;
• and
• a second input directly coupled to the transistor gate of the second NMOS component and the transistor gate of the second PMOS component, the second input configured to provide an enable signal,
• wherein the first NMOS component, the second NMOS component, the first PMOS component, and the second PMOS component are configured to provide an inverting output based on the input signal,
• wherein the number of fingers of the first NMOS component is greater than or less than the number of fingers of the first PMOS component to provide an imbalance between a drive strength of the first NMOS component and the first PMOS component, and
• wherein the imbalance is operable to cause a switching delay of the logic gate to be primarily dependent on one of the first NMOS component or the first PMOS component.