Memory controller with integrated test circuitry

A memory system instantiated on bonded dies, the memory system comprising:

• a controller die having a controller data terminal and a controller data-test terminal;
• a memory die bonded to the controller die and having a memory data terminal directly connected to the controller data terminal and a memory data-test terminal directly connected to the controller data-test terminal;
• the controller data terminal to communicate a data signal from the controller die of the bonded dies to the memory data terminal of the memory die;
• the controller data-test terminal to communicate a data-test signal from the controller die to the memory data-test terminal of the memory die;
• and
• at least one gating transistor on the memory die, the at least one gating transistor to gate the data signal from the controller data terminal on the controller die responsive to the data-test signal from the controller data-test terminal on the controller die.

A method for testing a memory controller integrated on a first die and bonded to a memory device integrated on a second die, the method comprising:

• generating a data-test signal on the first die;
• communicating the data-test signal from the memory controller on the first die to the memory device on the second die;
• communicating a data signal from the memory controller on the first die to the memory device on the second die;
• gating the data signal using the data-test signal to produce a delayed data signal;
• and
• capturing the delayed data signal using a sequential element on the first die or the second die.