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US 11,298,795 B2Granted
Polishing pad, process for preparing the same, and process for preparing a semiconductor device using the same
AssigneeSKC solmics Co., Ltd.
InventorsSunghoon Yun, Hye Young Heo, Jang Won Seo
Life of this patent
Estimating the term…
Abstract
Embodiments relate to a polishing pad for use in a chemical mechanical planarization (CMP) process of semiconductors, a process for preparing the same, and a process for preparing a semiconductor device using the same. In the polishing pad according to the embodiment, the size (or diameter) and distribution of a plurality of pores are adjusted, whereby the polishing performance such as polishing rate and within-wafer non-uniformity can be further enhanced.
Claims6
A polishing pad, which comprises a polishing layer comprising a plurality of pores,
- wherein the total area of the pores per unit area (mm2) of the polishing surface is 40% to 60%,
- the Dq value represented by the following Equation 1 is 5 μm to 15 μm,
- the Dsk value represented by the following Equation 2 is greater than 0.3 to less than 1, and
- the Dku value represented by the following Equation 3 is greater than 1 to less than 5:
- D
- q
- =
- ∑
- i
- =
- 1
- n
-
-
- d
- i
- 2
- n
- [
- Equation
-
-
- 1
- ]
- D
- sk
- =
- 1
- nD
- q
- 3
-
- (
- ∑
- i
- =
- 1
- n
-
-
- d
- i
- 3
- )
- [
- Equation
-
-
- 2
- ]
- D
- ku
- =
- 1
- nD
- q
- 4
-
- (
- ∑
- i
- =
- 1
- n
-
-
- d
- i
- 4
- )
- [
- Equation
-
-
- 3
- ]
- in Equations 1 to 3, d is a value obtained by subtracting the number average diameter of the plurality of pores from each pore diameter, and n is the total number of pores per unit area (mm2).
74 more elements
Dependencies are inferred from the claim text.