Low-power digital signal processing

A device, comprising:

• one or more sensors that, in operation, generate a multi-bit sensor signal;
• one or more processors;
• and
• frequency analysis circuitry communicatively coupled to the one or more sensors and to the one or more processors, the frequency analysis circuitry including:
• a circular register configured to store a representation of a first encoded sinusoid;
• a set of multiple logical gate blocks that are each configured to multiply, via one or more bitwise operations, each of multiple bits of the multi-bit sensor signal with a pulse train corresponding to a value of the first encoded sinusoid;
• and
• a logic circuit coupled to the circular register and the set of multiple logical gate blocks, the logic circuit configured to generate, based on the first encoded sinusoid and on the multi-bit sensor signal, an output signal indicating an approximate value of the received input signal multiplied by the first encoded sinusoid.

A method, comprising:

• storing a representation of a first encoded sinusoid in a first circular register;
• multiplying, via one or more bitwise operations, each of multiple bits of a received input signal with a pulse train corresponding to a value of the first encoded sinusoid;
• and
• generating, based on the first encoded sinusoid and on the received input signal, an output signal indicating an approximate value of the received input signal multiplied by the first encoded sinusoid.