Processing system, related integrated circuit, device and method

A device comprising a plurality of processing systems, wherein each processing system of the plurality of processing systems comprises:

• a timer circuit configured to generate, in response to a clock signal, a system time signal comprising a plurality of bits indicative of a time tick-count;
• a processing circuit configured to:
• receive the system time signal from the timer circuit,
• detect whether the system time signal reaches or exceeds a given reference value, and
• start execution of a given processing operation when the detection indicates that the system time signal has reached or has exceeded the given reference value;
• an error code calculation circuit configured to compute a first set of error detection bits as a function of the plurality of bits of the system time signal transmitted to the processing circuit;
• a first error detection circuit configured to:
• compute a second set of error detection bits as a function of the plurality of bits of the system time signal received by the processing circuit,
• compare the first set of error detection bits with the second set of error detection bits, and
• generate a first error signal when the comparison indicates the first set of error detection bits does not correspond to the second set of error detection bits;
• and
• a trigger generator configured to generate a trigger signal comprising a trigger when the system time signal increases by a given amount, and a watchdog timer configured to generate a third error signal when a time between two consecutive triggers in the trigger signal is greater than a given first maximum time, or
• a further timer circuit configured to generate a fourth error signal when a time between two consecutive triggers in the trigger signal is not between a lower threshold and an upper threshold.

A method of operating a processing system, the method comprising:

• generating via a timer circuit of the processing system a system time signal;
• computing a first set of error detection bits as a function of bits of the system time signal using an error code calculation;
• transmitting the system time signal and the first set of error detection bits to a processing circuit of the processing system;
• computing a second set of error detection bits as a function of the bits of the system time signal received by the processing circuit of the processing system using a first error detection circuit;
• comparing the first set of error detection bits with the second set of error detection bits, and when the comparison indicates that the first set of error detection bits does not correspond to the second set of error detection bits, generating a first error signal;
• computing a third set of error detection bits as a function of the bits of the system time signal using a second error detection circuit;
• comparing the first set of error detection bits with the third set of error detection bits;
• generating a second error signal when the comparison indicates that the first set of error detection bits does not correspond to the third set of error detection bits;
• and
• detecting whether the system time signal reaches or exceeds a given reference value, and when the detection indicates that the system time signal has reached or has exceeded the given reference value, starting execution of a given processing operation of the processing circuit of the processing system.