Synchronous divider based on cascaded retiming

A synchronous divider circuit with time-synchronized outputs, the synchronous divider circuit comprising:

• a plurality of divider stages, each of the plurality of divider stages comprising a D-flip-flop circuit and a respective retiming flip-flop circuit, wherein an output terminal of the retiming flip-flop circuit of a current divider stage of the plurality of divider stages is connected to an input of the D-flip-flop circuit of a next divider stage of the plurality of divider stages, and
• wherein the current divider stage of the plurality of divider stages comprises an additional retiming flip-flop circuit, wherein the output terminal of the retiming flip-flop circuit of the current divider stage of the plurality of divider stages is connected to an input terminal of the additional retiming flip-flop circuit of the current divider stage of the plurality of divider stages,
• wherein an output signal of the additional retiming flip-flop circuit of the current divider stage of the plurality of divider stages and an output terminal of the retiming flip-flop circuit of the next divider of the plurality of divider stages stage are time-synchronized with respect to each other.