Cross-phase detector based phase interpolator
AssigneeApple Inc.
InventorsJiaping Hu, Craig B. Byington
Life of this patent
Estimating the term…
Abstract
Embodiments relate to a phase interpolator cell. The phase interpolator cell includes a multiplexer configured to select between a first pull-up network and a second pull-up network. The first pull-up network includes a first pull-up transistor controlled by a first clock signal and is connected between a first input of the multiplexer and a first power supply. The second pull-up network includes a second pull-up transistor controlled by a second clock signal and is connected between a second input of the multiplexer and the first power supply.
Claims20
A phase interpolator cell, comprising:
- a first tri-state inverter having a control input receiving a first clock signal, an enable input receiving a first enable signal, a first power supply terminal, a second power supply terminal, and an output terminal;
- and
- a first multiplexer configured to select a first pull-up network when a select signal has an active value, and select a second pull-up network when the select signal has an inactive value, the first multiplexer having:
- a selection input receiving the select signal,
- an output coupled to the first power supply terminal of the first tri-state inverter;
- a first input coupled to the first pull-up network having a first pull-up transistor, the first pull-up transistor having a first terminal coupled to a first power supply and a second terminal coupled to one of the control input of the first-tri-state inverter and the selection input of the first multiplexer,
- a second input coupled to the second pull-up network having a second pull-up transistor, the second pull-up transistor coupled to the first power supply, the second pull-up transistor receiving as a control signal a second clock signal.
A phase interpolator cell, comprising:
- a pull-up network comprising:
- a first pull-up transistor receiving a first clock signal as an input;
- a second pull-up transistor receiving an enable signal as an input, a drain of the second pull-up transistor coupled to a source of the first pull-up transistor;
- a third pull-up transistor receiving a select signal as an input, a drain of the third pull-up transistor coupled to a source of the second pull-up transistor;
- a fourth pull-up transistor receiving a second clock signal as an input, a drain of the fourth pull-up transistor coupled to a source of the third pull-up transistor;
- a fifth pull-up transistor receiving an inverse of the select signal as an input, a drain of the fifth pull-up transistor coupled to the source of the second pull-up transistor.
A method for generating an output clock signal comprising:
- enabling a first tri-state inverter when a first enable signal is asserted, the first tri-state inverter receiving as an input a first clock signal and enabling a second tri-state inverter when a second enable signal is asserted, the second tri-state inverter receiving as an input a second clock signal;
- selecting a first pull-up network when a select signal has an active value and selecting a second pull-up network when the select signal has an inactive value, the first pull-up network coupling a power supply terminal of the first tri-state inverter and a power supply terminal of the second tri-state inverter when the first pull-up network is closed, the second pull-up network coupling the power supply terminal of the first tri-state inverter and the power supply terminal of the second tri-state inverter when the second pull-up network is closed.
Dependencies are inferred from the claim text.