Cycle borrowing counter
AssigneeWestern Digital Technologies, Inc.
InventorsTianyu Tang, Venkatesh prasad Ramachandra
Life of this patent
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Abstract
Circuits and systems for generating counter signals are provided herein. A circuit may comprise a shift register having a series of flip-flops. Each of the flip-flops of the series may be coupled to a clock. The shift register may generate a borrowing clock signal using an output of a flip-flop of the shift register, and a transition of the borrowing clock signal may be advanced by a number of clock cycles based on a position of the flip-flop of the shift register. The circuit may further comprise a clock divider circuit having a number of divide-by-N counters and a number of flip-flops. A divide-by-N counter may be coupled to a flip-flop of the shift register, and a flip-flop of the clock divider circuit may be coupled to one of the divide-by-N counters and to the clock.
Claims22
An asynchronous counter circuit comprising:
- a shift register comprising a series of flip-flops, wherein each of the flip-flops of the series is coupled to a clock, wherein the shift register generates a borrowing clock signal using an output of a flip-flop of the shift register, wherein a transition of the borrowing clock signal is advanced by a number of clock cycles based on a position of the flip-flop of the shift register;
- and
- a clock divider circuit comprising a number of divide-by-N counters and a number of flip-flops, wherein a divide-by-N counter is coupled to a flip-flop of the shift register, and wherein a flip-flop of the clock divider circuit is coupled to one of the divide-by-N counters and to the clock.
An asynchronous counter circuit comprising:
- means for generating a borrowing clock signal based on a clock signal, wherein a transition of the borrowing clock signal is advanced by a number of clock signal cycles;
- means for dividing the borrowing clock signal in a number of successive division stages to generate a counter output signal;
- and
- means for sampling, at a transition of the clock signal, the counter output signal.
A system comprising:
- a counter circuit configured to receive a clock signal;
- a series of logic gates configured to receive the clock signal and an output signal of the counter circuit;
- and
- an adjustable delay circuit configured to receive an output of the series of logic gates.
Dependencies are inferred from the claim text.