Lane adaptation in high-speed serial links

A method of performing lane adaptation for adaptive equalizer circuitry in a serial communications channel, the adaptive equalizer circuitry comprising a continuous time equalizer (CTE) and a discrete time equalizer (DTE), the method comprising:

• for each of a plurality of values of a CTE setting, responsive to which a filter characteristic of the CTE is selected:
• adapting the DTE by adjusting tap weights of at least one discrete time filter in the DTE according to an error minimization;
• and
• determining a figure of merit for an input signal filtered by the CTE at the CTE setting value and the adapted DTE in combination;
• selecting one of the plurality of values of the CTE setting responsive to the figure of merit values;
• and
• conditioning received input signals with the CTE at the selected setting value and the adapted DTE for that selected CTE setting value.

A method of adapting a discrete time equalizer (DTE) including at least one discrete time filter having a plurality of tap weights, the method comprising:

• filtering an input signal by the DTE to produce a filtered output;
• quantizing the filtered output of the DTE to produce a digital symbol value;
• determining an error gradient from the digital symbol value in a current iteration;
• determining a convergence coefficient from the error gradient in a current iteration and an error gradient from a previous iteration;
• and
• updating tap weights of at least one discrete time filter from a previous iteration responsive to a product of the convergence coefficient and the error gradient from the current iteration;
• and
• repeating the determining and updating steps until a convergence criterion is met.