Systems and methods for control signal latching in memories

An apparatus, comprising:

• a memory array;
• a control logic configured to provide a sleep signal to the memory array;
• an input circuitry having an input and an output, the input of the input circuitry configured to receive the sleep signal from the control logic, and the input circuitry configured to operate in a first power domain;
• a latch having a latch input and a latch output, the latch input coupled to the output of the control logic, the latch configured to store the sleep signal, wherein the input circuitry is configured to be electrically isolated from a power rail of the first power domain before the sleep signal floats;
• and
• a delay line coupled between the latch output and the memory array.

A system on chip (SOC) comprising:

• a memory array;
• means for providing a sleep signal to the memory array;
• means for receiving the sleep signal from the sleep signal providing means, the sleep signal receiving means including a plurality of logic circuits operating in a first power domain and being configured to be electrically isolated from a power rail of the first power domain during a time period in which the sleep signal floats:
• means for storing a value of the sleep signal during the time period in which the sleep signal floats;
• and
• means for causing a propagation delay in transmitting the value of the sleep signal to the memory array.