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US 11,122,513 B2Granted
Power management integrated circuit, power management method, mobile device and clock adjusting method
AssigneeSamsung Electronics Co., Ltd.
InventorsJunghun Heo, Youngduk Kim, Joonseok Kim, Dongsuk Shin
Life of this patent
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Abstract
A power management approach for a mobile device includes comparing a battery provided power supply voltage to a reference voltage in order to generate an alarm signal. In response to the alarm signal the frequency of an operating clock applied to a system-on-chip is changed.
Claims19
An electronic device comprising:
- a power management integrated circuit (PMIC) configured to
- output a first alarm signal to a control signal line, when a level of a power supply voltage varies from a level higher than a first reference level to a level lower than the first reference level, and output a second alarm signal to the control signal line, when the level of the power supply voltage varies from a level higher than a second reference level to a level lower than the second reference level;
- and
- a System-on-Chip (SoC) configured to
- receive the power supply voltage from the PMIC;
- receive the first alarm signal and the second alarm signal from the control signal line;
- provide, in response to the first alarm signal, a first operating clock having a first frequency, and
- provide, in response to the second alarm signal, a second operating clock having a second frequency,
- wherein, the second reference level is lower than the first reference level, and the second frequency is lower than the first frequency,
- wherein the PMIC is further configured to generate a first reference voltage as the first reference level, and to adjust a level of the first reference voltage based on power management information provided from the SoC, and
- wherein the PMIC is further configured to store data associated with the power management information and includes a reference voltage generator which sets the first and second reference levels based on the power management information.
8 more elements
A System-on-Chip (SoC) configured to
- receive a power supply voltage from a PMIC,
- receive a first alarm signal from the PMIC through a control signal line, when a level of a power supply voltage varies from a level higher than a first reference level to a level lower than the first reference level,
- receive a second alarm signal from the PMIC through the control signal line, when a level of the power supply voltage varies from a level higher than a second reference level to a level lower than the second reference level,
- receive a source clock having a reference frequency, generate a first operating clock having a first frequency based on the source clock in response to the first alarm signal, during a first period, and
- generate a second operating dock having a second frequency based on the source dock in response to the second alarm signal, during a second period, the first period and the second period being different from each other,
- wherein the first frequency and the second frequency are lower than the reference frequency,
- wherein the SoC is further configured to provide power management information to the PMIC to adjust the first reference level, and
- wherein the PMIC is further configured to store data associated with the power management information and includes a reference voltage generator which sets the first amd second reference levels based on the power management information.
5 more elements
A System-on-Chip (SoC) configured to
- operate based on a first operating clock having a first frequency during a first period, in response to first alarm digital codes provided from a power management integrated circuit (PMIC), when a level of a power supply voltage varies from a level higher than a first reference level to a level lower than the first reference level, and
- operate based on a second operating clock having a second frequency during a second period, in response to second alarm digital codes provided from the PMIC, when the level of the power supply voltage varies from a level higher than a second reference level to a level lower than the second reference level,
- wherein a duration of the first period is different than a duration of the second period,
- wherein the SoC comprises a current control circuit configured to provide power management information to the PMIC to adjust the first and second reference levels responsive to a predicted or detected power event and to set clock ratios of a clock divider to provide the first and second operating clocks responsive to the first and second alarm digital codes, and
- wherein the PMIC is further configured to store data associated with the power management information and includes a reference voltage generator which sets the first and second reference levels based on the power management information.
2 more elements
Dependencies are inferred from the claim text.