Transmitter, receiver, transmitter/receiver, and transmitting/receiving system

A receiver that receives from a transmitter a serial data signal based on a plurality of signals including at least two types of signal groups having different transmission rates, the receiver comprising:

• a receiving unit having an input terminal that inputs a training pattern signal and the serial data signal transmitted from the transmitter, a first output terminal that outputs a recovered clock, and a second output terminal that outputs recovered data, the receiving unit being configured to perform training of clock data recovery based on the training pattern signal and to recover the clock and data based on the serial data signal transmitted from the transmitter after the training is completed;
• a frequency divider having an input terminal electrically connected to the first output terminal of the receiving unit and an output terminal that outputs a sampling clock faster than a transmission rate of the fastest signal of the plurality of signals, the frequency divider being configured to divide a frequency of the recovered clock from the receiving unit so as to generate the sampling clock;
• a deserializer having an input terminal electrically connected to the second output terminal of the receiving unit and an output terminal that outputs a parallel data signal, the deserializer being configured to generate the parallel data signal based on the recovered data from the receiving unit;
• a decoder having an input terminal electrically connected to the output terminal of the deserializer and an output terminal that outputs a decoded parallel data signal, the decoder being configured to generate the decoded parallel data signal based on the parallel data signal from the deserializer;
• and
• a latch circuit having an input terminal electrically connected to the output terminal of the decoder and an output terminal that outputs any of the plurality of signals, the latch circuit being configured to keep a level of each bit of the decoded parallel data signal from the decoder at a timing indicated by the sampling clock, and then, to output a signal of each bit as any of the plurality of signals.