Radar interface with enhanced frame signal

A synchronous communication interface, comprising:

• at least one data channel configured to carry a data signal comprising a plurality of data units;
• a control channel parallel to the at least one data channel, the control channel configured to carry a control signal for the at least one data channel;
• and
• a circuit configured to generate the control signal that includes control information that defines each of the plurality of data units in each data signal and further includes additional information,
• wherein the circuit is configured to vary a duty cycle of the control signal according to a mapping of the additional information to a plurality of discrete duty cycle states,
• wherein the control signal is a pulse width modulated (PWM) signal and the plurality of discrete duty cycle states are discrete pulse widths corresponding to the duty cycle of the control signal, and
• wherein each first transition edge of the control signal indicates an end of a current data unit of the plurality of data units in each data signal, and each second transition edge of the control signal defines the duty cycle of the control signal corresponding to the additional information.

A method of synchronous communication, the method comprising:

• synchronously transmitting at least one data signal comprising a plurality of data units, in parallel with a control signal for the at least one data signal;
• and
• generating the control signal that includes control information that defines each of the plurality of data units in each data signal and includes additional information, including varying a duty cycle of the control signal according to a mapping of the additional information to a plurality of discrete duty cycle states,
• where each period of the control signal is synchronous with a length of a corresponding data unit of the plurality of data units.

A synchronous communication interface, comprising:

• at least one data channel configured to carry a data signal comprising a plurality of data units;
• a control channel parallel to the at least one data channel, the control channel configured to carry a control signal for the at least one data channel;
• a clock channel parallel to the at least one data channel and the control channel, the clock channel configured to carry a clock signal used for synchronizing communications between a transmitter and a receiver;
• and
• a circuit configured to generate the control signal that includes control information that defines each of the plurality of data units in each data signal and further includes additional information,
• wherein the circuit is configured to vary a duty cycle of the control signal according to a mapping of the additional information to a plurality of discrete duty cycle states.