Encoding and decoding methods, apparatuses, and devices

An encoding device, comprising:

• at least one processor;
• and
• a computer-readable storage medium comprising instructions that, when executed by the at least one processor, configure the encoding device to:
• encode first data in a first encoding manner to generate a first encoded sequence;
• encode second data in a second encoding manner to generate a second encoded sequence, wherein a quantity of bits comprised in the first data is greater than a quantity of bits comprised in the second data, and a quantity of bits comprised in the first encoded sequence is equal to a quantity of bits comprised in the second encoded sequence;
• perform Four-level Pulse Amplitude Modulation (PAM-4) modulation on an input signal to generate a symbol sequence, wherein the input signal comprises the first encoded sequence and the second encoded sequence, the first encoded sequence corresponds to a high bit of the input signal, and the second encoded sequence corresponds to a low bit of the input signal;
• and
• the symbol sequence;
• wherein the first data comprises 6448 bits, and the second data comprises 5668 bits;
• or
• the first data comprises 5324 bits, and the second data comprises 4700 bits;
• or
• the first data comprises 27436 bits, and the second data comprises 19600 bits.

A decoding device, comprising:

• at least one processor;
• and
• a computer-readable storage medium comprising instructions that, when executed by the at least one processor, configure the decoding device to:
• receive a first symbol sequence, wherein the first symbol sequence is generated after a second symbol sequence is transmitted to the decoding device by using a transmission medium, the second symbol sequence is obtained by performing Four-level Pulse Amplitude Modulation (PAM-4) modulation on an input signal, the input signal comprises a first encoded sequence and a second encoded sequence, the first encoded sequence corresponds to a high bit of the input signal, and the second encoded sequence corresponds to a low bit of the input signal;
• demodulate the first symbol sequence to obtain a first to-be-decoded sequence;
• decode the first to-be-decoded sequence in a first decoding manner to obtain first data;
• demodulate the first symbol sequence to obtain a second to-be-decoded sequence, wherein a quantity of bits comprised in the first to-be-decoded sequence is equal to a quantity of bits comprised in the second to-be-decoded sequence;
• and
• decode the second to-be-decoded sequence in a second decoding manner to obtain second data, wherein a quantity of bits comprised in the first data is greater than a quantity of bits comprised in the second data;
• wherein the quantity of the bits comprised in the first to-be-decoded sequence is 6500, and the quantity of the bits comprised in the second to-be-decoded sequence is 6500;
• or
• the quantity of the bits comprised in the first to-be-decoded sequence is 5376, and the quantity of the bits comprised in the second to-be-decoded sequence is 5376;
• or
• the quantity of the bits comprised in the first to-be-decoded sequence is 27556, and the quantity of the bits comprised in the second to-be-decoded sequence is 27556.