US 11,121,707 B2 · Programmable clock skewing for timing closure

Abstract

In one embodiment, an integrated circuit may be designed using a library of clocked circuits that have programmable clock delays that may be inserted on the clock input to the clocked circuits. During the design process, timing paths which are challenging due to significant variations across operating states, process corners, and/or temperature may be met by using the clocked circuits with programmable delays and inserting a delay control circuit that programs the delays based on the current operating state, process corner used to manufacture the integrated circuit, and/or temperature. That is, different delays may be selected by the delay control circuit depending on inputs that identify the operating state, the process corner, and/or the temperature. Because the clock delay is intentionally skewed, the timing of the path may be different at different operating states, temperatures, or process corners and thus may meet timing by changing the clock skew during operation.

Claims20

Dependent claims

An integrated circuit comprising:

a plurality of programmable delay circuits coupled to a clock input and having a delay input, wherein a first programmable delay circuit of the plurality of programmable delay circuits is configured to select a first delay based on a value on the delay input, and wherein a second programmable delay circuit of the plurality of programmable delay circuits is configured to select a second delay different from the first delay based on the value, and wherein the plurality of programmable delay circuits are configured to delay the clock input to generate respective clock outputs based on the respective first delay and second delay;
and
a delay control circuit coupled to the delay input, wherein the delay control circuit is configured to generate the value on the delay input based on a combination of an operating state indication identifying an operating state of the integrated circuit and a process indication identifying a process corner at which the integrated circuit was manufactured.

An apparatus comprising:

a clocked circuit having a clock input, wherein the clocked circuit is configured to perform a specified operation based on a first clock, and wherein the clocked circuit comprises a delay circuit coupled to the clock input and configured to delay a second clock on the clock input to generate the first clock, wherein an amount of the delay is selectable based on a delay input to the clocked circuit;
and
a delay control circuit coupled to the delay input of the clocked circuit and configured to generate a value on the delay input to select the amount of the delay, wherein the delay control circuit is configured to map a combination of at least a first indication of an operating state of an integrated circuit and a second indication of a process corner in effect when the integrated circuit implementing the apparatus was manufactured to the value, wherein the mapping is predetermined based on static timing analysis performed during a design of the integrated circuit prior to manufacture of the integrated circuit, wherein the delay control circuit comprises a table programmed with data that is determined via the static timing analysis, and wherein the delay control circuit is configured to read the data from the table to map the combination of the first indication and the second indication to the value.

Dependencies are inferred from the claim text.

Programmable clock skewing for timing closure

Life of this patent

Programmable clock skewing for timing closure

Life of this patent

Abstract

Claims20